I'm new to ARM microcontrollers and currently learning from the book "The designer's guide to cortex-M Family" by Trevor Martin. One of the odd things I've found is that I can't find many of the register's description such as SCB, PRIGROUP and many others on my device's datamanual or datasheet, but are present on my project libraries such as stm32f10x.h or core_cm3.h . Where I can find a complete source for registers? I tried http://infocenter.arm.com but it lacks the integrity of a manual and is more of a look up table and also I don't know what am I missing.
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\$\begingroup\$ Real registers are R00 through R99 (Cortex M4, I believe from memory, has R00 through R26, or some more, but those are also PC, SP, etc, or maybe those were R22 through R26). All else is read from an address range, which is outside of the core. It is customary for the chip vendor, ST in this case, to document what they put where and how they call it in their libraries. In fact, even KEIL's libraries use the vendor datasheet's naming and groupings. \$\endgroup\$– AsmyldofMay 16, 2016 at 1:20
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\$\begingroup\$ You might find the Reference Manual (www2.st.com/resource/en/reference_manual/dm00124865.pdf) more useful. \$\endgroup\$– brhansMay 16, 2016 at 2:16
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\$\begingroup\$ Thank you for your comment, I searched both this manual and datasheet but none contain the registers mentioned in the book. \$\endgroup\$– AliAMay 16, 2016 at 4:45
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\$\begingroup\$ @Asmyldof - That is the stack frame, which includes the architectural core registers R0-R15, as well as the FP state. The M-class architecture has many more architected registers which are memory mapped, these cover functions which are usually mapped in the co-processor space in other ARM architectures. \$\endgroup\$– Sean HoulihaneMay 19, 2016 at 7:57
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\$\begingroup\$ @SeanHoulihane Fair enough. There's a reason I didn't post it as an answer. But a Register mapped through the AHB/APB bus system is not truly a register in sense that they lie inside the core (and as such are "ARM's responsibility to document its location") and have canonical access, as the memory mapped system also features possible wait and synchronisation states that reduce the reliability of execution time, branch timing, load and store ... euh... canonicality??, etc. \$\endgroup\$– AsmyldofMay 19, 2016 at 16:30
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You can probably find what you are looking for in this ST document PM0253: STM32F7 Series Cortex®-M7 processor programming manual
The System Control Block (SCB) registers are architected, which is why they are mostly common with the Cortex-M3 (and where you should find much more documentation or examples). The reference manual for the particular processor will detail only the features which are specific to that processor.
answered May 16, 2016 at 21:47
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\$\begingroup\$ Feel free to mark the question as 'answered', this will help other people who think about providing an answer. Or wait a while and see if any beter answers are provided - up to you. \$\endgroup\$ May 19, 2016 at 7:51