Xilinx ISE ROM memory error

Question

Ive defined for my project a Single-Port ROM, using the Block Memory Generator of ISE tools. It appears as part of my project, but i'm having a error message implementing my top module. wich says:

ERROR:HDLParsers:709 - "C:/Users/Neander/Project/SinHandler.vhd" Line 56. memory_sin is not an entity name

Here's my .vhd:

memory: entity work.memory_sin -- BRAM with the sin values 
    port map(
    clka => clk,
    addra => mem_addr,
    douta => dout);

Answer 1

Where is memory_sin defined?

It looks like you haven't got the file with it in in your projects (or maybe it's too far down the list, so hasn't been analysed by the time you've tried to use it).