I have been trying to create a FSM using the excitation equations I developed. I have not had much luck. The circuit has no output.
I DO NOT WANT TO USE 'TYPE' and custom state types. That is the easy way out. Please don't tell me that's what you would do! Its probably what I would do too. I am trying to force myself to learn new methods.
Below you will find my process for the sequence "2314". I set up my DE2 so the push buttons were each assigned a number, ie X(0) is push-button 0 or number "1".
I found out the program would need 5 states (3 FF) using a Moore machine. If there is no input on the state ("0000") then the input should hold. I decided to use D flip flops for this experiment for ease of transitions. Turns out its not so straight forward! Thanks for your help.
My equations for the D flip flops are as follows (derived from state diagram/ transition table) They may not be simplified completely, sorry!
d0 = Q2'.Q0'.(X1.Q1'+ X2.Q1)
d1 = Q2'.(X2'Q1.Q0' + X3.Q1'.Q0)
d2 = x0.Q2'.Q1.Q0
z = Q2.Q1'.Q0'
You will find the VHDL code below. The component is also shown below. The current VHDL file is just one of my many failed attempts. The simulation does not have an output, therefor z is a constant '0'.
library ieee; use ieee.std_logic_1164.all; entity sequencedetecttwo is port ( x : in std_logic_vector (3 downto 0); clk : in std_logic; z : out std_logic ); end entity sequencedetecttwo; architecture arch of sequencedetecttwo is signal q : std_logic_vector (2 downto 0); signal d : std_logic_vector (2 downto 0); component dflipflop is port ( clk, d : in std_logic; q : out std_logic ); end component; BEGIN dff0 : dflipflop port map (clk => clk, d => d(0)); dff1 : dflipflop port map (clk => clk, d => d(1)); dff2 : dflipflop port map (clk => clk, d => d(2)); p0 : PROCESS(clk, q) BEGIN d(0) <= q(0); d(1) <= q(1); d(2) <= q(2); IF (clk'EVENT AND clk = '1') THEN q(0) <= not q(2) and not q(0) and ((x(1) and not q(1)) or (x(2) and q(1))); q(1) <= not q(2) and ((not x(2) and q(1) and not q(0)) or (x(3) and not q(1) and q(0))); q(2) <= x(0) and not q(2) and q(1) and q(0); END IF; END PROCESS p0; z <= q(2) and not q(1) and not q(0); END ARCHITECTURE arch;
And the flip flop component:
library ieee; use ieee.std_logic_1164.all; entity dflipflop is port ( clk, d : in std_logic; q : out std_logic ); end entity dflipflop; architecture arch of dflipflop is begin p0 : process (clk) begin if (clk'event and clk = '1') then q <= d; end if; end process; end architecture arch;