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I'm currently working on developing myself a computer based on the Motorola 68000 CPU and am currently working on the RAM interface. Since I want a basic multitasking OS, I want to use 1 MB of RAM. SRAM of that size is hideously expensive (around $25) but SDRAM of the same size and speeds exceeding what I need are much cheaper.

The question is this - What would I need to do to make SDRAM work with a MC6800? I know that it needs a refresh clock, so would that clock need to be my system clock (20 MHz) or my bus clock (System Clock/4 = 5 MHz)? What else do I need to look out for if I want to use SDRAM?

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I could be wrong, but I thought that SDRAM had more in common with DRAM than static ram. Specifically, if it uses multiplexed addressing, this will add complexity to your design. Anyway, with a 68K, you might get away with as little as 128K, like the original Mac had. If you happen to have cache-RAMs from a 486 vintage PC MB, those are usually 32Kx8 static, and relatively fast for 68K purposes. Four of those get you a nice 128K. But of course, if you want to produce more than one of these, that's not such an option. – JustJeff Feb 5 '12 at 23:19
True, you've got a point that I could survive off of 128K, but the main usage for this will be as a video frame buffer of sorts, in which application I want my 68k to render stuff into it, then my video card will run the chip at 4x the bus clock and DMA it's data to it's display memory. – Tristan Seifert Feb 5 '12 at 23:36
Ok, yeah. You don't want to mess around with 32K chunks trying to get to 1M+ – JustJeff Feb 5 '12 at 23:41
I can't answer your question completely, but I will point out that SDRAM does have a MINIMUM speed. If you run it lower than the minimum speed then it won't operate properly. This has something to do with the DLL (Delay Locked Loop). It might be possible to disable that so it'll run slower, but you'll need to keep that in mind. – David Kessner Feb 6 '12 at 0:01
@DavidKessner, only DDR types have a DLL, which can be disabled. In principle, DRAM cell leakage aside, I don't see why there would be a lower limit on operating frequency. – mng Feb 6 '12 at 7:59

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Sounds like a very educational project.

Typically, DRAM manufacturers specify that each row must have its storage cell capacitors refreshed every 64 ms or less.

My understanding is that you can use any one of the following 4 ways to keep the DRAM refreshed:

(a) My understanding is that all SDRAM has an internal on-chip timer that automatically refreshes the SDRAM when the SDRAM is placed in self-refresh mode and the clock to the SRDRAM is stopped. My understanding is that most simple systems don't bother with self-refresh mode, and instead use one of the other methods of refreshing DRAM:

(b) Some systems have special refresh hardware that periodically pauses the CPU, performs a refresh, then resumes the CPU.

(c) A few systems have a special "refresh interrupt" -- a timer signal periodically triggers a hardware interrupt, and the software in the interrupt handler does a refresh, and returns. (Some systems interrupt once every 64 ms, and the interrupt handler reads N bytes -- one byte from every DRAM row -- refreshing all the DRAM in one whack, then returns. Other systems interrupt once every 64/N ms, increment a row counter and read one byte from that DRAM row, then return). The "refresh interrupt" approach requires the least amount of hardware. Alas, a "refresh interrupt" has the drawback that minor bugs in the refresh interrupt software, or bugs in any other software that delays the refresh interrupt too long, cause weird difficult-to-reproduce problems elsewhere when memory becomes corrupted.

(d) Many early computer systems had special DMA video hardware that pauses the CPU, reads video data from the DRAM, and sends it to the video hardware. Many of them are set up such that the process of reading out all the video data, as a side effect, also reads at least 1 byte from every row of DRAM, indirectly refreshing all DRAM.

p.s.: Are you actually using a (effectively) 32-bit 68000, like the original Macintosh and Palm Pilot? If so, you may find it useful to check out the Minimig project, which uses a 68000 (and lots of SRAM), and the FPGA "soft cores" that execute the 68000 instruction set.

Or are you actually using an 8-bit Motorola 6800? If so, I highly recommend you check out the N8VEM Home Brew Computer Project.

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I am using the 16-bit 68000. Soft cores are one way of doing it, but I just like using the real chip a little better. Anyways, if I'd use this as video RAM at 60 FPS, the refresh would not be an issue, would it? Essentially I'm always accessing the RAM once every 16.67 ms. But then I can also just build an SDRAM <-> 68k bus interface into the FPGA. – Tristan Seifert Feb 9 '12 at 4:16
Yes. As long as you read at least one byte from each and every row (perhaps as a side effect of reading out the video data) in each 64 ms, then you don't have to do anything extra for refresh. – davidcary Feb 9 '12 at 22:27

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