This sort of delay scales inverse-linearly with clock speed as long as there are no interupts or similar running (ie double clock speed and delay halves).
This is useful: PIC delay routines.
To work out how many loops are needed you 1st need to know the number of clock cycles or uS per instruction at the clock speed used.
For the PIC that you have shown, most instructions take one "unit" of time.
This will vary among processor families.
Some take 4 crystal clock cycles per instruction, some take 1, some take more.
Assume you know Tw = basic instruction unity time at W Mhz.
In a PIC most instructions execute in Tw at W Mhz where Tw is usually 4/F_Mhz in the older style 14 bit core PICs. .
BUT check this for the processor you are using.
In a PIC the decfsz skip instruction takes one time uinit if the test fails (register is non zero) and two tun=me units if the test passes - gegister is zero and skip occurs.
Some processors may take one unit if test fails or passes or two whether it fauls or passes or ... - check what applies for the processor you are using.
So here the main timing loop is 3 time units usually and 4 units only when the register reaches zero.
Work out the basic unit time (say for nop instruction) at clock speed W Mhz and one mS then needs a count of x in 'movlw x' of
If a NOP took 0.5 uS then
- Count = 1000/0.5/4 = 500.
As an 8 bit counter can only count to 255, if variable_temp is 8 bit then this count is too large and a double byte counter is needed.
Something more like below.
Here you have inner and outer loops.
Each inner loop runs for K_Count_Low loops and the inner loop is called K_Count_High times. Counters are 8 bit so should be set to <= 255.
Maximum delay is ~~~= 255 x 255 x 3 x Tw.
Outer loop hanl=dling , included nops etc change this. Seeing exactly how is part of learning how this all works.
decfsz CounterLow, 1
decfsz CounterHigh, 1
Call "We are the Borg of Pentium. Division is futile! We will approximate you"