I need to production test the SRAM. As I see it, I have two options:
- Write an SRAM driver directly from the FPGA (without involving the Cortex).
- Route the Cortex memory pins through the FPGA to the memory.
Reading through the specs of the SRAM, it seems that writing an SRAM driver for the FPGA is a relatively difficult task. I am therefore inclined to go with option 2. However, I was told that there may be latency issues if I naively bridge up the Cortex to the SRAM.
How can I deal with those potential latency issues? Are there other difficulties arising from option 2 that I might be overlooking?