What is hold time violation?

I am currently reading about Pulsed Latch Circuit. And there is a frequent mention of "hold time violation". Like:

For latch, "...data must be held for a longer period of time, increasing the likely number of hold time violations".

Please explain what hold time violation is in the context of Latches.

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A hold time violation is when you don't cuddle with your wife long enough! –  user3624 Apr 8 '12 at 17:04

A edge-triggered latch (flipflop) ideally samples the data line instantaneously on one of the edges of the clock. However, nothing is truly instantaneous, so the data must be valid for some finite amount of time around the clock edge. The time it must be fixed before the clock edge is called the setup time, and the time it must be fixed after the clock edge is called the hold time.

Hold time violation is a violation of the hold time requirement. If the datasheet says the minimum required hold time is 10 ns and you change the data 5 ns after the clock edge, then you have committed a hold time violation and there is no guarantee which data value will end up on the flipflop output.

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Thank you for explaining hold time. But what is Hold time violation? Is it when data isn't valid for enough (hold) time? –  Vinayak Garg Apr 8 '12 at 4:14
@VinayakGarg - Basically. If you latch immediately after the inputs to the latch change, you may either latch the old or the new value into the latch. Basically, while the input is transitioning and for a (generally very) short period of time afterwards, the behaviour of the latch output is indeterminate in the event of the latch being triggered, and as such the output state cannot be predicted (and in extreme cases the latch may even oscillate!). –  Connor Wolf Apr 8 '12 at 6:19
@FakeName: It's possible for a device designer to ensure that, after specified time following a clock pulse, there will be no more rising edges (but if the output is high, there may be a falling edge). One may also do likewise with highs and lows reversed, or even have a device with three output states (high/low/indeterminate) with a guarantee that a report of "high" or "low" will be valid. This does not eliminate metastability problems, however, because the output might switch from "indeterminate" to "high" or "low" just as the next stage is trying to sample it. –  supercat Apr 9 '12 at 20:32

Olin has been clear, but I would add some details about the Pulsed Latch Register, and why this architecture may have different Hold Time requirements respect to other flip-flops.

First: the difference between latch and flip-flop

As you probably know, a latch is a circuit which in the basic form has an input, an output and a clock; when the clock is at a certain value - say high, for a positive latch - the latch is transparent, which means that the output replicates the input. When the clock is at the other level - low in this case - the output is held at the value it was before the clock commuted.

The flip-flop has the same pin configuration, but has a difference: it holds the value with the clock both high and low, and samples the new value on the edge (positive or negative) of the clock.

Pulsed latch flip-flop

A pulsed-latch flip-flop is nothing else than a normal latch, where the clock is driven by a very short pulse; in this way, the time in which the latch is transparent is very short, and it in facts behaves like a flip-flop.

Moreover, if a circuitry is used to create the pulse from a normal square wave clock, the whole circuit behaves really as a flip-flop.

Hold time violation

The problem is that if you have a certain technology process, you will have more or less a maximum speed at which you can commute a signal, due to the conductivity of the driving gate and the input capacity of the following one. If you consider a pulsed latch, the pulsing signal will commute to the transparent value, stay in that level for satisfying the setup time of the latch, and then commute again in a time that constitutes the hold time.

So the time in which the input must be held in order to sample it properly is equal to the duration of the pulse corresponding to the sampling, which is about double the time required by the edge triggering flip-flop. Hence the increase in the hold time violations

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+1 for explaining the difference in flip flop, latch and pulsed latch. Thanks! –  Vinayak Garg Apr 8 '12 at 17:59
@VinayakGarg just passed through that :D –  clabacchio Apr 8 '12 at 18:00