# Why can't regs be assigned to multiple always blocks in synthesizable Verilog?

The accepted answer to this question notes that "every reg variable can only be assigned to in at most one always statement". It's clear that in a lot of cases assigning a reg to multiple always blocks is meaningless. However, it's seems that there could be hardware-meaning instances of a reg in different always blocks.

For example, what if a same reg is assigned to always @(posedge clk1), always @(posedge clk2) where clk1, clk2 never beat of the same time? There would be no race-condition.

Why is there a "hard rule" concerning regs in different always blocks?

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For example, what if a same reg is assigned to always @(posedge clk1), always @(posedge clk2) where clk1, clk2 never beat of the same time? There would be no race-condition.

The case you mention will not be synthesizable. The flip-flop that implements the reg can only be clocked from one source.

As an aside, I'd like to clarify that the rule about regs having affinity to always blocks affects synthesizability, not validity. Software simulator will handle assignments from different always blocks without any problems.

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What about always @(posedge clk), always @(negedge clk) ? – Rocketmagnet Apr 10 '12 at 10:10
@Rocketmagnet, that's the same problem. Flip-flops react to one of the edges. – avakar Apr 10 '12 at 10:18
DDR flip-flops (available in IO blocks of many FPGAs) react to both edges. But even then, there's only one input, so it doesn't make sense to have the logic split up into multiple blocks. always @(posedge clk or negedge clk) or just always @clk would make sense. Even so, I'm not sure if any tools will synthesize those -- I have always explicitly instantiated the library block instead. – The Photon Apr 10 '12 at 15:36
@ThePhoton, that is my experience as well with Altera FPGAs: special peripherals (including DDR transceivers) are black-box modules, which can be instantiated into your design. – avakar Apr 10 '12 at 15:51

Although you may know that two clock edges will never arrive simultaneously, the synthesizer can't assume that. It's possible to construct a reasonable-cost circuit which will latch D1 on the rising edge of C1, and D2 on the rising edge of C2, provided that rising edges of C1 and C2 are always sufficiently separated. On the other hand, a pair of "always" blocks would indicate that such a circuit should also correctly and without glitches handle the case where the latch start out low, D1 and D2 are both high, and C1 and C2 arrive in arbitrary sequence, with arbitrary time between them. Even if a synthesizer could generate such a thing, the circuit cost would be more than double what would be needed to handle the case where C1 and C2 are always disjoint.

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