Your temperature sensor doesn't use just 1 wire to communicate, it uses 2. The clock wire is equally important as the data wire in communicating correctly.
The I2C bus is fairly complex, especially if all its bells and whistles are implemented. Luckily most chips don't implement every capability, and that's why datasheet-level documentation is often inconsistent. For complete and definitive information, you can get the full specification from NXP.
It is unclear to me how collisions can be avoided.
If the temperature sensor is the only other device on the bus, your FPGA will always be the master in the communication protocol. That means you control the clock signal, and you will always know whether the slave is allowed to drive the bus at any given moment.
Typically, you would write a state machine in your FPGA that manages the data in and out of the slave device, and knows when to send data out and when to receive data in.
Note that some slave devices will also assert control of the clock signal at certain specific times in the transaction, as described by the standard. They will do this to "stretch" the low periods of the clock and give themselves time to complete a measurement or calculation before the master starts clocking out the actual data. If your master design doesn't account for this, it could cause a "collision".
What happens when the same inout wire is driven by both the source and the master?
Since I2C devices can only drive low, it generally won't damage either chip if there's a conflict. When you want to send a logic '1', you don't drive the line high, you put it in high-Z state and let an external resistor pull it up. If the slave drives a '0' at the same time, there won't be any damage to either device.
What is the best way to model send-acknowledge cycles over one pin in Verilog?
Your Verilog won't "model" a send-acknowledge cycle. It will describe logic that generates the correct signals from the master device.
If you want to simulate the protocol before committing to hardware, you would write a second module that has another state machine that responds to the master's signals and produces the correct signals for the slave device.