# Using if/else syntax for assign statements

I have a wire to which I assign a complex right-hand-side expression with lots of bitwise operations. This right-hand-side expression is quickly becoming long and hard to maintain.

Is there a way I could replace the bitwise operations by if/else or case statements to help readability and maintability?

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Can't you just define intermediate wires? Then you can also give your intermediate signals intelligible names, further improving maintainability... – vicatcu Apr 10 '12 at 12:22
Also, many people avoid it in C-family programming languages, but to be proficient in Verilog you must become familiar with the ternary operator ?:. – The Photon Apr 10 '12 at 15:31

Sure you can, just use the always @(*) construct (you need to make it a reg). You can handle inout ports easily too.

reg res;

 The problem is that I cannot make it a reg because it is an inout port. – Randomblue Apr 10 '12 at 12:20 I've edited. Note that you shouldn't be using inout ports for internal connections anyway. – avakar Apr 10 '12 at 12:24