How do I use VHDL generic parameters when I place a sheet symbol in Altium?

Question

I'm using Altium Designer Winter 09 to synthesise a design for an FPGA. This includes a VHDL-defined entity MyShifter that includes generic parameters so I can have it be reuseable:

library IEEE;
use IEEE.Std_Logic_1164.all;

entity MyShifter is

generic
(
       data_width : positive;
       pad_width : positive
);

port
(
    -- ...other ports...
    DataIn        : in std_logic_vector(data_width-1 downto 0)
);

-- architecture follows...

With any other VHDL entity I could just right click on a schematic and use Place » Sheet Symbol, and then synchronise the sheet entries with the ports defined in VHDL. Altium will, later on, automatically generate the higher-level VHDL that maps ports to other ports and I don't have to worry about it.

When I try this with my entity-with-generics, I end up with sheet entry labelled DataIn[-1..0]. This is unsurprising, since I haven't "told" Altium what data_width actually is.

My question is: how do I tell Altium what the generic parameters data_width and pad_width are for a particular instance of MyShifter?

Answer 1

I'm not sure a good solution exists. You could add a second VHDL file that instantiates your first VHDL file's entity with the appropriate generic map. Then you could just place that second-level VHDL file onto the schematic.

Not ideal, but it maintains reusability, as you can just make new second-level files for every different size you want, and you only have to change the first-level file to affect all instantiations.

Answer 2

Have you tried adding it as a parameter to the sheet symbol?

Double-click on the sheet symbol, Go to the parameters tab, and add a parameter data_width. I would guess you want it of type INTEGER.

I'm kinda guessing here. I don't really use Altium with logic synthesis.

You may have to correct the sheet-entry labels manually after you add a parameter (or maybe just recompile the project).

---

Alternatively:

I know you can define project variables, but I don't know if they are presented to the VHDL synthesis system. If data_width is used in multiple places (and is the same everywhere), it may be worth trying.

Project >> Project Options >> "Parameters" tab.
It does not have the data-type options of the sheet-symbol, as described below, so it's possible that the VHDL synthesis system does not see project parameters.