# Meaning of the data input pins of a DAC

I'm trying to understand what each of the 10 data input pins of a DAC mean. The datasheet for the AD9761 I am using is available here.

The pins' description is given as follows (see page 10):

Each DAC consists of a large PMOS current source array capable of providing up to 10 mA of full-scale current, IOUTFS. Each array is divided into 15 equal currents that make up the four most significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose values are 1/16 of an MSB current source. The remaining LSBs are binary weighted fractions of the middle bits’ current sources. All of these current sources are switched to one of two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches.

I am confused about a few things here.

1. "Each array is divided into 15 equal currents" -> Why 15? The four MSBs have 2^4 = 16 combinations.

2. "equal currents" -> Why are the currents equal? Does it mean that 1000_0000_00 is the same as 0100_0000_00? Why do that?

3. "The remaining LSBs are binary weighted fractions" -> What is a binary weighted fraction?

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You have two levels of DAC decoding the two most significant groups of 4 bits; for each the output is built summing the current from the sources according to the binary decoded value of the 4 bits:

1. 15 sources, because the value 0000 means that no source is giving current;

2. Considering the output, 10.... is equal to 01.... but the fact is that you have the current sources active depending upon the input bits (see no. 1): if you have 0100, you'll have 4 current sources active;

3. binary weighted DAC is an architecture in which you use resistors with power of 2 values (you can use also switched capacitors or others); you have an op-amp where a reference voltage is feeded through these binary weighted resistors, that are switched accordingly to the input code.

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Thanks. Do you mean "binary weighted DAC" as opposed to "binary weight ADC"? –  Randomblue Apr 11 '12 at 13:38
@Randomblue yep :) that's what we are talking about, right? :) –  clabacchio Apr 11 '12 at 13:40

I don't think page 10 is the best description of the operation of these bits. You would be better served to look at the bottom left of page 11:

DAC TRANSFER FUNCTION

Each I and Q DAC provides complementary current output pins: IOUT(A/B) and QOUT(A/B), respectively. Note that QOUTA and QOUTB operate identically to IOUTA and IOUTB. IOUTA will provide a near full-scale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 1023), while IOUTB, the complementary output, provides no current. The current outputs of IOUTA and IOUTB are a function of both the input code and IOUTFS and can be expressed as $$I_{OUTA} = (DAC\;CODE/1024)\times I_{OUTFS}$$ $$I_{OUTB} = (1023 - DAC\;CODE)/1024\times I_{OUTFS}$$ where: DAC CODE = 0 to 1023 (i.e., decimal representation)

Note that 0 to 1023 is 10 bits -- presumably set by the data input pins. The paragraph on page 10 is describing the internal implementation (which may still be useful information for some applications).

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Thanks. Does I and Q bear any relation with the formula given in the paragraph "Analog QAM" given here? –  Randomblue Apr 11 '12 at 13:46
@Randomblue -- Yes, I expect most people using this DAC are probably using it for some sort of quadrature modulation, considering how it is marketed by ADI. You could use it for other applications, though. –  Justin Apr 11 '12 at 13:59