# Are Verilog reals synthesisable?

Is the Verilog real data type synthesisable for a generic Xilinx FPGA? If not, what alternatives do I have for real number manipulation in synthesisable Verilog?

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 It depends on what tool you're using for synthesis... – Ben Voigt Apr 11 '12 at 14:55 @BenVoigt: I'm using ISE. – Randomblue Apr 11 '12 at 15:00