Undefined behaviour in a PSRAM read memory transaction

Question

I am reading the datasheet of a PSRAM (available here). Looking at the timing diagram for burst reads (page 10, figure 8), there is a "undefined behaviour" for a half-cycle on the DQ pins, before the data words D0, D1, D2 and D3 arrive.

What could be the cause for this undefined state of the DQ pins? Is this common for PSRAMs?

Answer 1

That means you can't count on what the pins are. They could be high, low, hi-z. This is common for memory parts that have a latency of more than one state.

To answer @stevenh below, it says that before the unknown time you can count on it being hi-z. During the unknown time is what I said above true.