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I was impressed by your solution of my previous problem. So, I think you may help me with this image

I have made huge circuit with OpAmps and couple of active and passive components, but I suppose that it can be solved much easier. Thank you!

Upd: I was said that the solution is wrong and this problem needs much theoretical than practical approach. So, I divided input voltage on 2 signals, now I need to process and concatenate them. The questions are following: 1. Is there another way than integration to process first signal; 2. Actually I don't understand how to dump second signal without capacitor;enter image description here

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If this is homework, show us what you've already tried, and in what way isn't it working. – The Photon Apr 15 '12 at 18:54
@The Photon everything is working, but the scheme is creepy. – Yurgen Apr 15 '12 at 19:02
It's not huge. It looks fairly small. – Rocketmagnet Apr 15 '12 at 20:27
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Solved in what way? You haven't stated any question. – Olin Lathrop Apr 15 '12 at 20:31
Your timing diagram bears no resemblence to your schematic. What are you trying to integrate or convert? I know how to integrate and dump, but what is the purpose? – Tony Stewart Apr 17 '12 at 6:46
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2 Answers

YOu can Integrate and Dump with a counter and reset where the frequency of the clock has been converted to the voltage of the input w.r.t. ref.

In an "optimal data discriminator" used in receivers, integrating the data over the entire bit period and then sample it and dump to restart it is the theoretical optimal solution to detect binary noisy data to give the best BER for a low SNR condition.

Just a SWAG on my part IF you wanted to think about using an I&D cct for converting noisy analog data to binary. Or it could be used in data collection instrumentation such as to measure the volume from a flow meter on analog sensor level, where the integral is desired, such as measuring velocity from acceleration over a period of time with a known initial condition. Another SWAG. Most people start with simple 4016 cmos switches to dump the caps but then can get feedthru spikes.

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This might be what you are looking for (assuming you are still trying to solve this problem). This is stevenvh's answer drawn out as a schematic, and simplified by removing the AND gate.

Sin wave to square wave thingy

Rather than use two sin wave sources, here I am using a capacitor and resistor to create a little less than 90º phase shift. I'm not sure exactly how accurate you need this. Alternatively, you can just use the 90º phase shift voltage source you showed in your schematic.

These two signals are turned into phase shifted square waves by the comparators. If you use comparators with open-drain outputs, then you don't need the AND gate, as the outputs are basically half an AND gate each. You just need to add a pull-up resistor, and you're done.

Notes:

  • You will need comparators with an open-drain output.
  • There is no explicit hysteresis in this design. Either use a comparator with internal hysteresis, or add some.
  • If you really the output to be perfect, then you need exactly 90º phase shift, so you'll have to use the opamp differentiator that stevenvh mentioned in the previous question.
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1. If want to answer the other question, why don't you do it there? – stevenvh Apr 18 '12 at 13:09
2. phase shift of an RC low-pass filter is atan(\$\omega\$RC). It's frequency dependent but will never be 90°. Why are you using 560\$\Omega\$ and 2.2\$\mu\$F? – stevenvh Apr 18 '12 at 13:09
3. sin > cos for 180°, not 90°. I would have loved to see it so simple, but this doesn't seem to work. – stevenvh Apr 18 '12 at 13:10
@stevenvh - It's frequency dependent, but he specified 1kHz in the question. – Rocketmagnet Apr 18 '12 at 13:16
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No it isn't. What about the output's duty cycle? If I look at a sine and cosine on the same graph I see that sine > cosine between \$\pi\$/4 and 5*\$\pi\$/4, that's over 180°, or 50% duty cycle. The graph in the question shows 90°. Pity, I liked the idea. – stevenvh Apr 18 '12 at 13:35
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