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I'm using a MOSFET to buffer my signals from a CPLD. The signals travel external to the PCB using long (from 1m to 10m) wires and then come back to the same PCB - the wires are actually the component under test. The pull up resistor, R2, is situated on the input side of the PCB. I was probing my signals when I noticed that my fall time is very fast (4.4ns fall time) yet my rise time was 264ns. Here's my schematic of the buffer:

enter image description here

Here are some captures from my oscilloscope:

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The circuit actually works just fine. I've had a unit under long term testing and I've had zero issues so far. I am just curious what could cause asymmetrical rise/fall times. My theory is that it's because I'm using the MOSFET in open-drain configuration. The 1K pull-up resistor slows down the rising edge of the waveform and if I used a smaller resistor, the edge would rise quicker.

NOTE: Please ignore the ringing on the falling edge. I've asked a separate question regarding that.

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If you use a smaller resistor, your low output level will be higher, and you'll have more static consumption. But for ure it'll be quicker. – clabacchio♦ Apr 16 '12 at 10:40
Unless you need a fast rise time, you might be able to equalize the rise and fall times by increasing R1 and/or adding some capacitance from the Q1 gate to ground (the Q1 gate probably has some parasitic capacitance, so one could just add resistance; the effects would probably be more predictable and consistent, though with 100pF or so of added capacitance). That may help you avoid some of the apparent "ringing" on the falling edge, and may reduce RF emissions. Experiment starting with 10K resistance and 100pF and see what happens. – supercat Apr 16 '12 at 15:36
@supercat Would you say that increasing 1K is a better option or using schottkey diodes for clamping the over/under voltage during ringing? Please see this question: electronics.stackexchange.com/questions/30026/… – Saad Apr 16 '12 at 15:53
Increasing R2 will increase the time between a falling edge on Vin and a detectable rising edge on the output. The techniques I described for slowing down the gate of Q1 are likely to slow the falling edge more than the rising edge (the behavior depends on the characteristics of Q1); with the right delay on the gate of Q1, the rise and fall times could be more or less symmetrical. Note that the resistor I was suggesting you increase was the 100 ohms, not the 1K. – supercat Apr 16 '12 at 15:59

2 Answers

up vote 3 down vote accepted

Like Telaclavo says it's in the difference of the output drive when low versus high. When high the output sees a 1k\$\Omega\$ impedance, when low a few hundred m\$\Omega\$. This only causes the effect you're seeing if the output is capacitively loaded, if the capacitance is zero you would see the same rise and fall times. From the rise time you can even estimate the capacitance: the 99% level will be reached after about \$5 R C\$.

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stevenvh, why does the output see a 1K impedance when high and why is it a few mOhms when low? – Saad Apr 16 '12 at 10:35
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@Saad because you have different devices to pull hegh and low :) The resistance must be weaker than the MOS, otherwise you wouldn't have the low level. – clabacchio♦ Apr 16 '12 at 10:39
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@Saad - When the MOSFET is off we can pretend it's not there. Then there's just the 1k resistor through which a load can be charged. If the MOSFET conducts any charge on the load can be drained very fast to ground because of the MOSFET's low \$R_{DS(ON)}\$ (400m\$\Omega\$). – stevenvh Apr 16 '12 at 10:40
@stevenvh the load in this case would be the input pin of my CPLD? So basically a CMOS circuit which needs to be charged or discharged through my buffer circuit. So when the mosfet is off, the CMOS input is charged via the 1K resistor and hence it's low but when the MOSFET is on, the CMOS input discharges very quickly. Did I follow you or am I off base? – Saad Apr 16 '12 at 10:47
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@Saad - Correct, but don't let the scope's image mislead you. You're using a very short timebase, the input capacitance is probably a few tens of pF. The rise time is probably OK, it's just that discharging is a few orders of magnitude faster. – stevenvh Apr 16 '12 at 10:53
up vote 8 down vote

That's because you are actively (with the MOSFET) pulling down, but passively (with the resistor) pulling up. If you want a shorter rise time, either try a lower resistance value for R2, or use a totem-pole buffer (with two complementary MOSFETs, one to ground, and one to the supply), so that you will have a pulling effect in both levels. The easiest way to have a totem-pole buffer is to put there a high-speed CMOS inverter, with enough current capability to drive whatever your load is.

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