I tried to simulate a circuit with mosfets in LTspice, but it's still hard to understand how they work

What I observed:

For N-channel MOSFETs (as in the picture above)

a) Current flow through N-channel MOSFET transistor

1. Does not depend on V1's voltage
2. Depends on V2's voltage
3. Does not depend on the current charging the gate (from V2)

b) Voltage across R3 is never higher than V2 - V1 (even if R3 resistance goes to infinity) and it doesn't depend on the V1's voltage.

c) The current charging the gate is extremely low (about 0.0002fA).

For P-channel MOSFETs

a) Current flow through P-channel MOSFET transistor

1. Does not depend on V2's voltage
2. Depends on V1's voltage
3. Does not depend on the current charging the gate (from V2)

b) Voltage across R3 is almost equal with V1's voltage

c) The current charging the gate is extremely low and it's not constant.

Please tell me if I said something wrong.

EDIT: The only thing I don't understand is, considering the schematic in the picture above, why does the voltage across R3 can not be grater than 8V, no matter how big R3 resistance is? I expected it to be 9V with a big resistance.

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Clean up your descriptions. "V1's voltage" makes sense since V1 is a voltage source, but "V1's voltage 2" makes no sense. Similarly, the voltage "at" a two terminal device makes no sense. For a two terminal device you can talk about the voltage at each terminal relative to the implied 0 reference, or the voltage accross the device (between the two terminals). – Olin Lathrop Apr 30 '12 at 19:40
What about this behavior did you find unusual? If you were doing DC operating point simulations and were not dropping Vgs voltage below the saturation point, this is exactly what you should expect to see. – The Photon Apr 30 '12 at 20:41

I'll just answer the NMOS part of your question. The answers for PMOS are similar, so the explanation should carry over.

a) Current flow through N-channel MOSFET transistor

1. Does not depend on V1's voltage
2. Depends on V2's voltage
3. Does not depend on the current charging the gate (from V2)

As long as you are operating the MOSFET in saturation, this is exactly what you expect. The relevant graph from the datasheet for your device is this:

When the gate-source voltage (in your schematic the voltage between N4 and N5) is high enough, only the gate-source voltage has a strong effect on the current through the MOSFET; the drain-source voltage (controlled by V1 in your circuit) has very little effect.

If you reduce V2 low enough, and by small enough steps, you should be able to trace out the roll off in the triode region, where both V1 and V2 will affect the current.

c) The current charging the gate is extremely low (about 0.0002fA).

This is exactly what you should see. The gate of the MOSFET is effectively a capacitor, and at DC will conduct almost no current.

b) Voltage across R3 is never higher than V2 - V1 (even if R3 resistance goes to infinity) > and it doesn't depend on the V1's voltage.

Again this is roughly what you should see, but V2 - V1 is not the relevant parameter, the threshold Vgs of the FET is. If R3's value is increased at constant current, it will reduce the difference between N4 and N5 voltages. That is, it will reduce the gate-source voltage of the MOSFET, until Vgs hits its "threshold" when the FET pretty much stops conducting altogether. So if R3 goes infinite, the MOSFET is shut off, and no current flows through R3. Despite R3 having a very high value, the voltage across R3 then becomes 0.

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 Thank you for your answer! – Cristi May 1 '12 at 9:59

I think what you are seeing is a artifact of a corner case of the simulator. Ironically, you'd probably get about the same result with a real circuit, but for a different reason. That is because a real voltmeter has a finit resistance, so will load the drain even if it is otherwise not connected to anything.

When the source gets close to the gate voltage, the FET will be off. However, there is always some finite leakage. This leakage should eventually bring the source at least to the level of the gate. The source will be a very high impedance node in that case, so even a 10 MΩ resistor from source to ground in the form of a voltmeter will be enough to lower the drain voltage a significant amount.

So you're right in that the source should be higher, but it would take very specialized equipment to measure that.

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 Thank you !!!!! – Cristi Apr 30 '12 at 22:57 He's running a source follower and looking at the source voltage. V_R3 can of course only approach V2 at best. And the fact that he's worried about gate current at the FA level indicates that he's not really aware of it being a voltage driven device. – Russell McMahon May 1 '12 at 0:40 Telaclavo: Doh! I said "drain" in a bunch of places where I meant "source". Fixed. Sorry for the confusion. – Olin Lathrop May 1 '12 at 12:01

The gate is 9 V. The source is 8 V. If the source got higher, the Vgs would decrease below 1 V. As Vgs gets smaller the fet begins to turn off, reducing the current and lowering the source voltage. So it reaches a balance where the source voltage is high from lots of current but not so high to turn off/down the fet.

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 I will agree that books are often the best fit, i would suggest teaching the concept and giving a book as a reference for much further learning. Thanks for updating the post, wish you had flagged me to undelete sooner. – Kortuk♦ May 22 '12 at 14:24