# Clock circuit layout techniques

I am prototyping (point to point wiring only) a digital circuit with multiple shift register IC's to be clocked simultaneously at 500Khz. The distance between the clock source and the IC clock pins is going to be about 5 inches max. How should I lay this out to make sure it works?

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What do you mean by "simultaneously"? How exactly the same do you need the timing to be for the IC clock events? For example, "no more than 1 millisecond apart" or "no more than 100 femtoseconds apart"... –  The Photon May 12 '12 at 23:58
@Photon: The shift registers are daisey-chained together to make one big shift register of 128 bits so they have to be clocked together to meet the set-up and hold times for a clock frequency of 500 Khz. –  Fred Paine May 13 '12 at 0:14
@Photon: I'm using the NXP HEF4015 static shift register. –  Fred Paine May 13 '12 at 0:21
@Photon: I changed to the CD4015 Texas Instrument chip, it has a claimed zero hold time requirement and it is designed to be daisychained. I will use one clock buffer to drive all the clocks as you recommend. I will use the TC4424 line driver for this . –  Fred Paine May 14 '12 at 13:02
I don't know the TC4424, but if it can drive the capacitance of 4 (or wheatever) loads you should be okay. If you want to worry about EMC you might want to add a series resistor at the output to deliberately slow down the rise and fall times. But really if you need to prove out EMC with this proto you should build a PCB instead of doing point-to-point. –  The Photon May 14 '12 at 16:17

• Electrical signals on PWBs with e=4.2 the delay is about 5 ns/m. Your 5" = 127mm or 0.127m so prop. delay of 0.63nS is negligible.

added: PVC insulation of wire-wrap awg30 has about the same e = 4 and twisted pair 8~10 twists /" as I recall is around 150 Ω, characteristic impedance. Not so important at these slow speeds but do not bundle WW wire signals together. Crosstalk can make a large point-point network fail with WW wire. ( Had a bad experience in 1978, aircraft tech had to rewire backplane from tight WW bundles to direct random point-to point wiring to eliminate crosstalk glitches so my design would work. )

• Prop delay is a factor of sqrt(e)/c where c is the speed of light = 3*10^8 m/s

• Some people calculate sqrt(4.2)/c= 7 nS/m but the permittivity or dielectric constant, e drops with increasing frequency or inverse rise time, so most FR4 prop delay is 5 ns/m.

add: same is true with PVC permitivity

• Generally avoid 90deg corners on high speed clocks but your clock may not be high speed (<30 ns range) . __/

• Put a guard path of ground on either side of the track in horizontal or vertical plane. Check your fanout capacity of the clock driver. 555 may need to be buffered with '04

• If you want books on Design Rules for layout, there are IPC international standards for pad sizes for various parts and soldering methods, and lots of useful DRC guides.

I found these just now, and they may be useful;

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I had to look up "PWB", I'd never seen the term before. Assuming it means "Printed Wiring Board", what's wrong with "PCB"? That's what everybody uses. –  Federico Russo May 13 '12 at 5:09
@FedericoRusso, you guessed the acronym right. The usage comes about because until you place the components on the board, there's no circuit, just disconnected wires. So some consider "printed circuit board" an inappropriate term for an unstuffed board and use PWB instead. In some shops "PCB" is totally deprecated in formal usage and you'll see PWB for the board blank and PCA ("printed circuit assembly") or sometimes PCBA for the stuffed board. –  The Photon May 13 '12 at 5:45
@ThePhoton: wow, pernickety! :-) But you could also interpret PCB as a board to be used for a printed circuit, couldn't you? ;-) –  Federico Russo May 13 '12 at 6:00
In my experience, people say "PCB". This can mean a bare board or a stuffed board. Usually it's obvious from context which you mean, but when it's not you use "bare board", "stuffed board", "assembly" and the like. Statements like professionals never use "PCB" are just plain wrong, and more likely the result of someone wanting to promote their favorite usage by pretending it's a standard. –  Olin Lathrop May 14 '12 at 15:09
People still call them Plug and JACK instead of Plug & RECEPTACLE . a wrong term that is common, does not make it "right" is the same as PCB is still common, but that does not make it comform to the IPC or MIL-std-handbooks for proper terminology. –  Tony Stewart May 14 '12 at 17:21

At 500 kHz, you have a 2 us clock period, and you don't have to worry about set-up times.

Assuming you're using a 5 V power, supply the part you referred to has a hold time of 40 ns (min) and a propagation delay of ... well they don't specify a minimum but they imply a minimum of about 93 ns (for no capacitive load). That gives a 50 ns slack between the time the second shift register clocks in its input and the time that the first shift register output changes, invalidating the second shift register input.

If you just keep your clock lines reasonably short, you should have no problem with this design.

If you do have problems, then go back and figure out how to minimize the clock line impedance (keep a ground wire parallel to each clock wire), and finally if that doesn't work, start worrying about how to route the clock --- counter-propagating relative to the direction of data flow is probably best, but really with 50 ns slack it shouldn't matter at all.

EDIT

Wouter is absolutely right (in a comment to his own answer) that you must evaluate the "minimum propagation delay against the maximum required data hold time". And that nothing in the data sheet guarantees the circuit will work.

However, we should note also the data sheet gives a (typical) formula for the propagation delay as a function of load capacitance: 93 ns + (0.55 ns/pF)CL (for the worst case: t_PLH at 5 V Vdd). That means

1. You'd need have 0 load capacitance to (typically) get a prop delay as low as 93 ns. This number is only typical so you might see slightly lower numbers occasionally. But most likely you wouldn't see the number drop by half.

2. If it doesn't work you can add a small capacitor to the output to increase the delay. You might not get exactly 0.55 ps per pF of adjustment, but you won't simply get no adjustment at all.

I'm assuming, since you're using point-to-point wiring, this is a one-off circuit and a manual adjustment is a reasonable choice. For a mass-produced product you would want a much more sure solution than this.

EDIT 2

1. Somewhere you mentioned using buffers (plural) to drive the clock inputs of your shift registers. Be aware that the propagation delay differences between two buffers will cause much more timing difference between the clocks at your different shift registers than just about anything to do with layout.

If you care about clocking your registers simultaneously, I strongly recommend to use one buffer to drive all of them. But do be sure your buffer is able to drive the combined capacitive load of all the chips it's driving.

2. Working at 500 kHz and a circuit that's 5" in its longest dimension, transmission effects like stubs and shunts will be utterly undetectable. This circuit can be designed entirely satisfactorily considering the interconnect wires as lumped R L C elements (mostly C).

If you do something so crazy (like run the wire around the room before getting it back to its destination) that transmission line impedance matters, you have a problem because your CMOS outputs are not designed to drive transmission lines. For the love of Sweet Baby Ralph, don't overdesign what doesn't have to be overdesigned.

3. EMC. Again at 500 kHz and 5" circuit diameter, it's very unlikely to have any problem. The easiest way to cause a problem here is to overdesign your buffer chips so that your signals have faster rise/fall times than they need, in which case you could have an emissions problem. If you just stick to nice slow clock edges (but not too slow -- mind the max recommended slew rate spec Tony pointed out) you'll be good.

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@Photon: Would you recommend using a 30gage twisted pair(signal/ground) transmission lines from the clock (555) to the IC's or 30 gage wires run above a continuous ground plane serpantine style? –  Fred Paine May 13 '12 at 1:03
At these speeds what is limiting you is the ability of the clock source to drive a capacitive load. Either of your proposals will work fine at 5 inches. If you need to extend it to 5 feet, you'll need to start worrying. –  The Photon May 13 '12 at 1:29
@Photon: Thank you for helping me out! –  Fred Paine May 13 '12 at 1:44
Actually Set-up and hold times are used in conjunction with Rise/Fall times so clock pulse width is more important too , and frequency is just an overall factor. These numbers must be understood by any designer to avoid timing errors and race conditions. e.g. negative setup times for this device. –  Tony Stewart May 13 '12 at 7:40
I could use twisted pair for 5" distance and single wire is OK for short connections <3". If it was PECL, then it would all be twisted pair. The noise margin is high on CMOS and this is not an issue even if straight wire. But TTL & MOSFET motor driver current surges might have an issue with inductive wire. So keep that in mind. –  Tony Stewart May 13 '12 at 7:44

Theoretically, your design won't work because the chip requires a non-zero data-hold time (period in which the input data must be stable after the active clock edge), while the output of the previous chip has no guaranteed minimum data out delay (from the active clock edge to the output).

Whether this is a problem in practice depends on the actual data out delay. Note that this has NOTHING to do with the clock frequency.

If you have problem there are a number of possible solutions. The best is to use a chip that has a special delayed data out, intended for chaining (that output changes delayed, or even on the opposite clock edge). Example: CD4094, p3 of the datasheet show the extra register that is clocked by the inverted clock, to yield a half-cock delayed output suitable for daisy-chaining.

The second best is to use a chip that has a zero data-hold requirement. The 74HC595 , p11, has a typical hold time of -2, but note that the minimum is +3. Funny, a minimum that is lager than the typical vlaue, but it makes sense. This suggestion can be combined with the next suggestion.

The third best is to delay the data change (series resistor and/or capacitor to ground) and/or to feed the clock starting at the most downstream shift register (so the SRs will be clocked back-to-front). (This approach is a stopgap measure at best.)

An alternative that has some design impact is to invert the clock for every other SR (= feed the odd numbered chips with the inverted clock). There is some discussion of this approach on SE, but I don't recall where. It does lose you some SR outputs.

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Thanks for joining the discussion. If I cant daisey-chain static shift registers running this slow there must be something wrong with the universe. Let me go back and look at the timing chart. –  Fred Paine May 13 '12 at 9:27
Slow or fast has nothing to do with it, it is the data-hold that bites you. –  Wouter van Ooijen May 13 '12 at 9:35
How about just adding an AND gate(with imputs tied together) with a suitable propagation delay between the chips? –  Fred Paine May 13 '12 at 10:22
I'm just checked the data sheet for this chip and the propagation delays for the low to high and high to low transitions are about 6 times greater than the nominal hold time for this chip. I don't see a problem here unless I am missing something :-( –  Fred Paine May 13 '12 at 11:24
@Fred: Theoretically you must evaluate the minimum propagation delay against the maximum required data hold time. The datasheet I checked ( nxp.com/documents/data_sheet/HEF4015B.pdf ) does not show a minimum propagation delay. If you use the typical figures you end up with a design that works only typically. It is up to you (the designer) to determine whether that is sufficient. –  Wouter van Ooijen May 13 '12 at 15:03