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I have a product in volume manufacture where the embedded CPU is now obsolete.
I have to replace that CPU with a lower cost alternative. For political (and practical) reasons I don't have a choice which CPU to use.
The original CPU had a companion chip which provided a printer port. The replacement does not have that feature.

The printer port is/was used for debug purposes by a legacy (and very a old/obsolete) RTOS. I would love to change that OS, but due to the complexity, that is not going to happen before we stop prodution of the current design due to shortages.

The replacement CPU does not have a IEEE1284 port (otherwise known as EPP, ECP, LPT, SPP,printer etc)

I have hunted high and low and can't find an ASIC which implements IEEE1284 on a 3.3V PCI bus. The only parts I can find that ever were are also obsolete.

I can find VHDL soft IP, but the powers that be don't want an FPGA in the design, and in any case the cost of the IP is far too high.

So, (at the risk of being accused of 'shopping') is there manufacturer that still makes a 3.3V PCI IEEE1284 (sometimes called a SuperIO) ASIC device that can be bought at a low cost in relatively low production volumes for sale in (or import to) Europe?

TIA,

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Does it have to be over PCI? You can certainly still get USB -> LPT conversion devices. Or it might be possible to put a fast microcontroller on the PCI bus and have it implement the necessary behaviour. – pjc50 May 14 '12 at 9:33
The interface is for low level debug. I'm not even sure if the RTOS will have a USB driver for a generic USB-LPT port (I've not seen one) and even if it did, it would have to be installed early during boot, to make debug agailable at that time. In any case a USB miniport would use OS indirection to supply a printer port. Any chip has to be at the standard PC LPT1 IO address. – Jason Morgan May 14 '12 at 11:06
I think the suggestion of a fast micro on the PCI bus would go the same way as the FPGA route I would rather use. It's another programmable device and hence not liked by others. – Jason Morgan May 14 '12 at 11:09

2 Answers

up vote 1 down vote

I suggest you bit banging LPT port in code. AVR example can be found here. Alternatively you can make debugging via some new preffered interface, and then just for old debug devices make an intermediate hardware that will translate this new interface to old LPT interface. This will be good for the future, because you can drop LPT completely when RTOS finally gets a replacement.

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This won't work. The LPT port is used in ECP mode by the RTOS internals for debugging. It expects to use the 'standard' address of the LPT port. This address would on on PCI, ISA or LPC. Horrid, I know, but that's just the way it is. – Jason Morgan May 14 '12 at 11:03
up vote 1 down vote

You could use a CPLD chip to sit on the PCI bus and implement the ECP port. Yes it's going to need some verilog deign work, but there's decent PCI bus models on opencores to test against. It's often a single chip design, as you don't need configuration hardware required by an FPGA.

Here is an open-source project using a CPLD to implement an IDE adapter for ISA bus as a motivation: http://dangerousprototypes.com/2012/02/13/xt-ide-adapter-tested-and-working/

There are several people working on this stuff over in the Vintage Computer Forums http://www.vintage-computer.com/vcforum

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If he doesn't want an FPGA chances are that a CPLD is out as well. – stevenvh May 24 '12 at 9:27
The "powers that be" might not know the difference :-) – shuckc May 24 '12 at 9:35
Especially then it will be a no-no. You might get away with it if you explain it's something different completely. – stevenvh May 24 '12 at 9:38

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