Synchronise crystal oscillator with external short burst

Question

I am trying to generate a stable 4.43361875 MHz clock (i.e. PAL colourburst) synchronised to the colourburst of a PAL video signal.

In a PAL signal the colourburst is provided for only about 8-10 cycles near the beginning of each line. So, I need a way to start the oscillator immediately on the rising edge of this clock source so they are in phase with each other. Once started, it can free run to keep the colour reference frequency accurate for other parts of the system.

I've thought about using a low end PIC24EP64GP202 to do the timing stuff (thanks to its onboard PLL and easy availability), but I can't think of a way to get its oscillator to start on a rising edge input. Is it perhaps possible to "pulse" the crystal with this incoming colour burst (so it rings for a few cycles) and then let the PIC take over? Perhaps it's possible, once running, to change the phase of the system clock?

I've noticed the PIC has a rated 1024 cycle start-up time, but I wonder if that's simply the lock-out period in which the processor doesn't get any clocks but the oscillator still runs fine.

Answer 1

Not sure if you are still around or gave up, but in order to create a stable VCXO clock locked to the PAL chroma burst, you need a few timing signals like a "sandcastle" window detector to sample and hold the phase error during this period for the PLL to work.

So use this chip to get your clock and you are good to go.

Since a crystal has an extremely narrow bandwidth (BW) of 1/3000 of the centre frequency, that BW (~1KHz) will determine the best case low pass response delay and lock up time of the Xtal, however once many colour bursts are received or around 10mS of accumulated bursts) , it will stay in sync until the next horizontal line, so that only minor phase corrections can be done during the burst.

It is extremely difficult (but not impossible) to make a PLL lock up in one cycle and then be stable until the next burst. It would require precise measurement of frequency and phase with a 100x clock to get within 1%. using the horizontal sync with 2nS stability. The Horz Sync acts as a freq reference for another PLL loop from the same VCXO with less than 1ppm error and very low phase noise, which sounds easy, but is not cheap.

Answer 2

Depends what you are trying to do. With only a PIC to work with, I'd use an Injection locked LC oscillator or a PLL synced to Horizontal Sync with counter in PIC or CPLD. or stand TV decoder chip.. What is it for?