# VHDL debouncer circuit

I'm working in a digital engineering lab and I'm trying to figure out how this debouncing circuit works. It's provided as-is by Xilinx but I'm not quite sure why it does what it does. Any pointers, perhaps? Following is the VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Debouncer is
Port ( CLK : in  STD_LOGIC;

Sig : in  STD_LOGIC;
Deb_Sig : out  STD_LOGIC);
end Debouncer;
architecture Behavioral of Debouncer is
signal Q0, Q1, Q2 : STD_LOGIC := '0';

begin
process (CLK) is
begin
if (CLK'event and CLK = '1') then
Q0 <= Sig;

Q1 <= Q0;

Q2 <= Q1;

end if;

end process;

Deb_Sig <= Q0 and Q1 and (not Q2);

end Behavioral;

-
What do you understand? –  Kortuk May 20 '12 at 12:31
When trying to understand VHDL, it's always best to try to draw a diagram of what it's doing, either at the signal level or at the gate level, as Teleclavo shows below. For debouncing in general, it is important to know the characteristics of the incoming signal, which in turn determine the clock speed of an entity like this and the number of samples you ought to take. –  Kevin H May 20 '12 at 21:04

I believe, this debouncing circuit is for the active high input. It uses the three flip-flops. 1st flipflop accepts "sig" and output "Q0". 2nd flipflop accepts "Q0" and output "Q1". 3rd flipflop accepts "Q1" and output "Q2". This three flip flops implementation is to avoid/ignore any glitches at the input. It drives the output signal only if the input signal state (logic 0 or logic 1) is stable for atleast three clock cycles "3 x clk - rising edges".

-