In practice, you will never explicitly use one hot encoding. Rather, you should design your VHDL file so that you use enumerations instead of explicit states. This allows the synthesis tools that you use to generate your design to come up with their own preferred encoding. In a CPLD, this would probably be dense coding, because gates are more abundant than flip flops. In an FPGA, this would probably be one hot, because flip flops are more abundant. In other random cases, the synther might think that gray coding, or sequential coding, might be better.
However, to answer your question, how does this perform a rotation? (note I am using your original 3-bit state, even though your question regards 4 bit states)
Consider state = "001". Thus, state(1 downto 0) = "01". Also, state(2) = '0'.
Thus, when you do state <= state(1 downto 0) & state(2), you are doing state <= "01" & '0'. This now means state = "010"; a left rotation by one bit.
In plain language, to rotate an n-bit vector to the left by one bit, take the lower n-1 bits, and concatenate the MSB on the right side of it. In this example, it's taking the state(1 downto 0) bits, and concatenating state(2) on the right side.
In contrast, a right rotation would be represented as state <= state(0) & state(2 downto 1). This takes the LSB, and then concatenates the upper n-1 bits on the right side of it. For state = "001", this right rotation would be like state <= '1' & "00". This now means state = "100".