vhdl code: one hot encoding of state

if I am using one hot encoding for the states and want to go from S0 -> S1 -> S2 -> S3 -> S0

Apparently the following code does this. However I am not sure how the state assignment part works in the snippet (comments mention rotation of 1 bit...?)... can someone please explain HOW this rotation works ie. why the "&state(2)" etc. It would also be extremely helpful if you could provide a simple hardware representation of the code snippet.

process (clk) begin
if rising_edge(clk) then
if reset = '1' then
state <= S0;
else
--rotate state 1 bit to left
state <=
state(1 downto 0)
& state(2);
end if;
end if;
end process;


In the architecture we are told that S0 = 0001, S1 = 0010, S2 = 0100, S3 = 1000

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 There is no reason to be "clever" in your code writing. Write plainly and simply and let the tool optimize. Only when you are fighting for space should you start trying to code tricky like this. There is no value in state <= state(1 downto 0) & state(2) when a clearer and more easily understood case statement would get the same job done. – Andrew Kohlsmith May 22 '12 at 19:54

In practice, you will never explicitly use one hot encoding. Rather, you should design your VHDL file so that you use enumerations instead of explicit states. This allows the synthesis tools that you use to generate your design to come up with their own preferred encoding. In a CPLD, this would probably be dense coding, because gates are more abundant than flip flops. In an FPGA, this would probably be one hot, because flip flops are more abundant. In other random cases, the synther might think that gray coding, or sequential coding, might be better.

However, to answer your question, how does this perform a rotation? (note I am using your original 3-bit state, even though your question regards 4 bit states)

Consider state = "001". Thus, state(1 downto 0) = "01". Also, state(2) = '0'.

Thus, when you do state <= state(1 downto 0) & state(2), you are doing state <= "01" & '0'. This now means state = "010"; a left rotation by one bit.

In plain language, to rotate an n-bit vector to the left by one bit, take the lower n-1 bits, and concatenate the MSB on the right side of it. In this example, it's taking the state(1 downto 0) bits, and concatenating state(2) on the right side.

In contrast, a right rotation would be represented as state <= state(0) & state(2 downto 1). This takes the LSB, and then concatenates the upper n-1 bits on the right side of it. For state = "001", this right rotation would be like state <= '1' & "00". This now means state = "100".

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I think the logic is wrong... you've got a four bit state vector, but you are only using three of the bits in any logic. It is obvious that to cycle through the states all you have to do is shift the bits left by one with rotation right? Just make a table showing the state sequence desired:

S0 0 0 0 1
S1 0 0 1 0
S2 0 1 0 0
S3 1 0 0 0
S0 0 0 0 1
...


The hardware for this is just to wire the output of the 4-bit register back on itself with the lines crossed to get the affect above.

Namely: State(0) <= State(3), State(1) <= State(0), State(2) <= State(1), State(3) <= State(2)

The abbreviated way of stating that is to form a new vector from the old one like this:

NewState(3 downto 0) = { State(2 downto 0), State(3) }
State <= NewState


Not sure my syntax is perfect, but that's the gist of it I believe; I think what I wrote is something like a Verilog/VHDL mashup. Anyway, you just want to express running the wires back to the right place so the 1 shifts left and around each clock.

As @mng noted - the '&' operator concatenates bit vectors together, and does not perform a logical-and, as one might think.

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how exactly is "--rotate state 1 bit to left" part doing the shifting? In terms of the vhdl syntax? – rrazd May 22 '12 at 3:51
In VHDL, the '&' stands for concatenation. – mng May 22 '12 at 4:58
@mng I like Verilog's syntax for this better... seems abusive to use & as an operator that doesn't correspond in some way to the 'and' logic operation; anyway yes the VHDL syntax is the key to what the OP was asking (the code is still wrong though) – vicatcu May 22 '12 at 16:10
@vicatcu: Seems abusive, because you're used to C. However the BASIC-like language are all consistent in use of AND for the bitwise operator and & for concatenation of strings. – Ben Voigt May 22 '12 at 20:44
And ultimately, VHDL's syntax is far cleaner: state <= state ROL 1;. Unfortunately the code in the question didn't use that. – Ben Voigt May 22 '12 at 20:46