# Instantiate n times a given module

As a continuation to my previous question, is there a way, in Verilog, to instantiate n times a given module, without having to use n different lines:

myModule instance1();
myModule instance2();
myModule instance3();
...


Can I do "batch" instantiation in Verilog?

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 Can you bring over the required information from your previous question if it is needed? – Kortuk♦ May 23 '12 at 16:18

Ok, found it. Search here for the "generate statement":

Verilog 2001 generate statement allow to either instantiating multiple modules without typing them so many times or instantiating modules conditionally. You can use if-else to conditionally instantiate the modules. Also, if you want to instantiate the same module multiple times then better use for loop. This will save you lot of time.

The following code will do the job:

genvar i;
generate for (i = 0; i < n; i = i + 1) begin
myModule instance();
end endgenerate

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If you are going to write an answer, include a bit more detail. When that link goes dead, your answer will have no value. – Kellenjb May 23 '12 at 15:32
For the record, VHDL also has a generate statement. – ajs410 May 24 '12 at 18:53