Instantiate n times a given module

Question

As a continuation to my previous question, is there a way, in Verilog, to instantiate n times a given module, without having to use n different lines:

myModule instance1();
myModule instance2();
myModule instance3();
...

Can I do "batch" instantiation in Verilog?

Answer 1

Ok, found it. Search here for the "generate statement":

Verilog 2001 generate statement allow to either instantiating multiple modules without typing them so many times or instantiating modules conditionally. You can use if-else to conditionally instantiate the modules. Also, if you want to instantiate the same module multiple times then better use for loop. This will save you lot of time.

The following code will do the job:

genvar i;
generate for (i = 0; i < n; i = i + 1) begin
    myModule instance();
end endgenerate