# Putting linear feedback shift registers on FPGA's

I need to put seven 128bit linear feedack shift registers on a FPGA chip. Are there any FPGA's that can impliment this? Thank you.

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Any FPGA can do this! –  stevenvh May 24 '12 at 17:36
@Steve: I have no idea, I'm not familiar with these devices, but thank you. –  Fred Paine May 24 '12 at 18:00

Event the very smallest FPGAs, and most CPLDs can do this. Each element of the shift register needs a single FF element, call that 1/4 of a slice, the xor for the tap logic will go into the LUT. Look at your datasheets, anything with > 300 slices should do it. You'll need extra logic to pre-load a value, control reset and sample the outputs, and probably clock enable logic as you would not want it free-running with the global clock while you read the final state.

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@Shucke: Thanks for the info! What would be the best way to find someone to program the chip for me and how much would this cost, just ballpark figures? –  Fred Paine May 24 '12 at 20:31
FPGAs are expensive. The chip is at least $10, and you need non-volatile storage like a Flash chip to read it. You would be much better off using a CPLD instead. If all you need is an LFSR, then an FPGA is way, way overkill. You could probably fit dozens of 128-bit LFSR's into the smallest FPGA. – ajs410 May 24 '12 at 20:40 He needs 896 memory element to build his seven 128-bit registers. That doesn't fit in a small CPLD. And a large enough CPLD might cost quite a bit. For example, Altera 5M1270 is near$18 when bought from Altera...maybe \$10 through other channels or in higher volume. That's enough to pay for a lot more resources in an FPGA. –  The Photon May 24 '12 at 21:27
Whoa, I totally missed the seven in OP's post. That is entirely my bad, you're right, seven 128-bit LFSRs will probably not fit in anything but the largest CPLD. –  ajs410 May 24 '12 at 22:00

If you're working on Xilinx, have a look at XAPP 052. This app note describes a technique for implementing an LFSR on Xilinx devices that uses the LUT memory rather than individual flip-flops to implement an LFSR. This results in using maybe 1/10 or less resources to do what you want.

Probably other vendors' FPGAs have similar possibilities.

That said, for the current generation of FPGAs, even the 896 registers needed to build your seven 128-bit shift registers naively will require only very small fraction of the resources available. Even Lattice's "mini" ECP3 FPGA has 17,000 logic blocks, each with an attached register.

In a CPLD, you would need to think more carefully about this design. CPLD's with 10's or a couple of hundred registers are still common, and some vendors (I'm looking at you, Xilinx) haven't updated their CPLD families for many years. CPLD's with enough registers to do your design could cost as much as a much more capacious FPGA that you could also use to implement other logic in your design.

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@Photon: Great info, I guess the FPGA will be the way to go, I will have to study these things, I will probably be able to put my complete encryption system all on one chip. Go easy on Xilinx, they have the coolest name in all of electronics :-) –  Fred Paine May 24 '12 at 21:39
"Probably other vendors' FPGAs have similar possibilities." No. That's a Xilinx thing for a special mode of the LUT RAM. –  Brian Carlton May 24 '12 at 21:43
Lattice also has a "RAM-based shift register" library module in at least MachXO2 and LatticeSCM families; but their documentation is egregious --- it's not really stated explicitly how much resources are used --- presumably there's some benefit relative to just inferring a bunch or registers, though. –  The Photon May 24 '12 at 22:05