Power filter design

Question

In my circuit design, I use a power supply filter design commonly used in my company, i.e. a pi filter which has a big electrolytic cap(10uF), an inductor and a small ceramic capacitor(100nF) at the other end, for every module in my circuit. How should I design these values for an industrial grade design?

Answer 1

You're basically asking, how to design a power supply filtering and bypassing network. This question is really too broad to answer completely here, but I'll give some general ideas. Probably other answers will point out issues I've forgotten or alternative solutions.

I'll assume you're talking about a PC board design (as opposed to IC design or chassis system design).

The power supply filter has several responsibilities in your circuit:

1. Prevent the power supply's noise and interference received on the power supply lines from adversely affecting circuit operation.

2. Prevent switching noise from one IC in your circuit from adversely affecting it's own operation or operation of other ICs.

3. Prevent switching noise from your circuit from creating radiated emissions from the power supply lines.

In order to design your power supply network carefully, you will need to model each of the sources of noise, then use calculations or simulations to determine how each contributes to the effects I outlined; then determine a filter topology and component values that adequately constrain these effects.

Roughly speaking, the input (10 uF in your example) cap and inductor in your circuit are responsible for #1; The individual 0.1 uF caps at each IC are responsible for #2; and the 0.1 uF caps and inductor are responsible for #3.

Also, the importance of each issue depends on the details of your circuit:

• For a precision analog circuit, be especially wary of source noise affecting the circuit.

• For a digital circuit, be especially wary of generated emissions.

• For a mixed-signal circuit, consider the concerns of both analog and digital circuits, and also be especially concerned about noise generated by digital circuits affecting performance of analog circuits.

A couple of other considerations:

• You mentioned that your circuit uses an inductor in the top arm of the pi. A ferrite bead is often used in this location instead because its less likely to cause an oscillation due to resonance with capacitances in your circuit. On the other hand its often hard to specify a complete model for a ferrite bead and so difficult to predict its behavior with simulation.

• You mention a 10 uF electrolytic cap on the input. This is actually not a very large value. I've seen circuits with many 100's of uF in this location. However increasing this value also increases the inrush current drawn from the power supply when the circuit is turned on.

That said, the network you describe is a very common one that will be adequate for many situations. If you have a good reason to improve it, please ask more specific questions and we will try to assist you.

Answer 2

Depends on the output impedance of the previous stage, the input impedance of the next stage, and the cutoff frequency you want. Without all of that information your design will not be adequately constrained. You'll need to model it as an ideal voltage source, inline with an output impedance, in parallel with the first pi leg, in series with the top of the pi filter, in parallel with the second pi leg and the input impedance of the second stage.