# Clarification on what the max freq of PIC24FJ64 is?

I'm confusing myself a bit here. The following is taken from this datasheet:

High-Performance CPU:

• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz

Now I want 16 MIPS, which is its max speed. But that 32Mhz, is that the xtal freq or the internal clock freq?

I currently have an 8Mhz xtal selected, and by using the PLL X4, that should give me the 32Mhz, but I'm not sure if the FOSC/2 happens before or after.

What xtal would I need to get max speed out of this device ?

Edit: I believe my current configuration is correct. That an 8Mhz xtal with PLL x4 enabled will give me the 16MIPs i require and that the divide by 2 for the internal clock cycle happens after the PLL.

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As an aside, note that the singular of MIPS is MIPS, not MIP. Laugh all that you want, but I've seen it in print. – stevenvh Jun 7 '12 at 16:38

The datasheet is correct, as they usually are. The PIC 24F family can run at a maximum instruction cycle rate of 16 MHz, which can be expressed as 16 MIPS (Million Instructions per Second). This processor requires 2x clock over the instruction rate, so the maximum clock is 32 MHz. You can achieve 32 MHz clock with a 8 MHz crystal and the 4x PLL. That will result in 16 MHz instruction clock.

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 Thats what I thought as well. Thanks Olin! – efox29 Jun 7 '12 at 16:14

You have clock cycles and instruction cycles. Here one instruction cycle requires two clock cycles. So 32MHz is the highest clock frequency, 16MHz is the highest instruction rate.

FWIW, most RISC definitions require a single clock cycle per instruction, which makes that PIC non-RISC.

trivia
The original 8051 had a 12MHz clock for a 1MHz instruction cycle. So it needed 12 clock ticks for the most simple instructions. Other instructions even took longer. Later Clock/6, Clock/2 and Clock/1 designs of the 8051 appeared.

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 I've always considered RISC to mean most instructions execute in a single instruction cycle, having nothing to do with the number of internal clock cycles it takes to make one instruction cycle. The contrast is with complicated instruction sets where instructions took a variety of instruction cycles, and sometimes were even variable depending on addressing modes and the like. PICs are RISC in that sense, whereas a x86 is not. – Olin Lathrop Jun 7 '12 at 17:20 @Olin - No problem with that, but the word "RISC" doesn't appear anywhere in the datasheet. It doesn't have to, but most manufacturers would see it as an asset. If their microcontroller does 1MIPS/MHz they will surely mention that. – stevenvh Jun 7 '12 at 17:27