I'm confusing myself a bit here. The following is taken from this datasheet:
- Modified Harvard Architecture
- Up to 16 MIPS Operation @ 32 MHz
Now I want 16 MIPS, which is its max speed. But that 32Mhz, is that the xtal freq or the internal clock freq?
I currently have an 8Mhz xtal selected, and by using the PLL X4, that should give me the 32Mhz, but I'm not sure if the FOSC/2 happens before or after.
What xtal would I need to get max speed out of this device ?
Edit: I believe my current configuration is correct. That an 8Mhz xtal with PLL x4 enabled will give me the 16MIPs i require and that the divide by 2 for the internal clock cycle happens after the PLL.