# PLL - why compare phases not frequencies

I have a question about PLL's. The aim of PLL is to get two signals with the same frequencies (there can be a shift in phases, as I understand). So, in this case, why do you use a phase detector to compare phases, and NOT just compare frequencies?

thank you

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In most cases, the best way to tell if the frequency of the feedback waveform precisely matches the frequency of reference waveform is to observe whether the two waveforms maintain a fixed phase relationship. If the frequency of the feedback waveform is slightly higher than that of the reference wave, its phase will to lead that of the reference wave form by an increasing amount each cycle. Likewise if its frequency is lower than the reference, its phase will lag each cycle. If the reference waveform is reasonably stable, trying to maintain a phase lock will yield a very stable frequency lock.

There are times when maintaining a phase lock is difficult or counter-productive, such as if one needs to generate a stable frequency whose long-term average matches that of a "warbling" reference. In that case, the fact that a frequency-locked loop wouldn't track the reference frequency as tightly as a phase-locked loop would not be a disadvantage, since the whole purpose of the loop in that case would be to avoid having the warbling in the reference passed through to the output. In general, though, the tighter response of phase-locked loops is preferable to the looser response of frequency-locked loops.

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From a more theoretical angle, frequency is the time derivative of phase. Equivalently, phase is the time integral of frequency. So, when a phase detector is used to control frequency via a VCO, there is an integration around the loop. Or, roughly speaking, a low-pass filtering effect.

As supercat points out, the advantage gained is the rejection of "warbling" or even glitches in the reference.

Many years ago, with a freshly minted BEE, I used a PLL to solve a problem where glitches on the backplane clock, due to, for example, hot plugging cards, (this was a digital loop carrier), caused a particularly sensitive card to "lock up", dropping any active call in progress. The PLL rejected the glitches, producing a stable clock for the line card, that, on average, was frequency locked to the backplane clock.

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I can't think of any frequency-locked loops that are more responsive than phase-locked loops. You are correct that the phase is an integral of frequency, but in a typical PID loop the integrator can "wind up" by a significant amount. By contrast, every time a frequency difference is integrated up to a 180-degree phase difference, the phase-vs-frequency response gets inverted. Though I guess that even if one used a counting circuit which could keep track of "phase differences" beyond 180 (or even 360) degrees one could still call such a device a "phase-locked loop". –  supercat Jun 27 '12 at 15:15