There are many ways to create ROM's inside of an FPGA using VHDL. But honestly it is borderline too big to really put into an answer here. Without cutting down your question into something more manageable it will be difficult to give a complete answer.
But, let me start by giving you an idea about what kinds of things are possible (a.k.a. what I've done with Xilinx ISE)...
At compile time your VHDL code can read a text file that has the binary representation of the contents of your ROM. Each line of the text file would have something like "001011101" that represents the contents of that word of the ROM (or initialized RAM). Note: The last time I tried this, which was several versions of ISE ago, you were limited to binary "text". I know that other VHDL synthesis tools might support something more complex and useful.
At compile time you can calculate the contents of ROM (or initialized RAM). In one project of mine, I populate the ROM with a compile-time-calculated sine wave table. In a different project I calculate the coefficients for a filter and store that in the ROM. I should emphasize that the contents of the ROM are calculated at compile time, not simply read from another file or other canned source of data. In this way the data will change to reflect anything relevant, like the bit depth of the sine wave table or the number of taps of the filter. I can even do my calculations in floating point and then convert it to std_logic_vector before putting them in the ROM.
In my VHDL code I can specify in a nice way what the ROM contents should be. Essentially listing out what the contents similar to this: rom_contents := ("01001", "10111", "00111", ..); You can even use VHDL functions to convert non-std_logic_vector data into std_logic_vectors, making your VHDL code more readable or easy to maintain.
There are several key things to knowing how to do this:
The primary key is to simply know VHDL inside and out. Know how it's data types work and how to manipulate them. There is nothing Xilinx specific here, as these things are FPGA manufacturer independent (although not all VHDL sythesis tools support all kinds of VHDL constructs).
The next key is to look at example code. Simply going to the Xilinx web site and search for "ROM Coding techniques" will return lots of information. Even the Xilinx XST documentation has lots of info in there. Most of that info is in the 10+ megabyte XST users guide PDF, so know that in advance before trying to open that gigantic file.
If you gave me something specific I could dig up some example code. And by specific, I need to know exactly what you mean by "compile-time generated constant memory". There is no way I can give you more generic examples of ROMs, that would just be too much. But a very specific example is possible.