I'm looking at switching a rough hardware design from using a master-IC generated MCLK signal for I2S to using a standalone MCLK generator circuit. I'm a bit new to this area of electronics, but from what I've read I'd need to create a buffered clock signal to avoid any drops in clock between chips. What's the rationale for this? Are there any good example circuits you could point me in the direction of?
I've done a rough design for a 12.228 MHz clock with an inverter. It'd be great to get some critique before trying to lay it!