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I'm looking at switching a rough hardware design from using a master-IC generated MCLK signal for I2S to using a standalone MCLK generator circuit. I'm a bit new to this area of electronics, but from what I've read I'd need to create a buffered clock signal to avoid any drops in clock between chips. What's the rationale for this? Are there any good example circuits you could point me in the direction of?

Edit -

I've done a rough design for a 12.228 MHz clock with an inverter. It'd be great to get some critique before trying to lay it!

MCLK generator design

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Please don't add NCs to the schematic symbol. With two inputs it looks like an opamp instead of an inverter. – stevenvh Jul 12 '12 at 9:34
Good point.. thanks! – njt Jul 12 '12 at 9:39
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It's not the NCs that bother me, it's the three R5s and two C16s! – MikeJ-UK Jul 12 '12 at 10:47
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@Mike - Ha! Hadn't even noticed that, so I didn't understand the comment to my answer :-). I think it's a way of saving parts. – stevenvh Jul 12 '12 at 11:07
Hah sorry! I just realised. I just threw it into something already open so i could draw it easily... thanks for your help! – njt Jul 12 '12 at 12:53

2 Answers

up vote 3 down vote accepted

In your schematic the R5 in series with C16 don't serve any purpose. Your loop to the crystal should come from after R5, like this:

enter image description here

Then R5/C16 cause the required phase shift, and form a low-pass filter preventing the oscillator to oscillate at the 3rd or 5th harmonic. Also, connecting the inverter's output directly to the crystal will overdrive it.

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AH. I've just noticed that, thanks. That's actually an input mistake when i was copying it into altium. – njt Jul 12 '12 at 10:09
Which R5 and C16 would that be then? :( – MikeJ-UK Jul 12 '12 at 10:48
@Mike - Fixed ! – stevenvh Jul 12 '12 at 11:09
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You mainly need to buffer a clock if it is going to lots of places or very far. Since you are only going from the clock generator to the I2S chip, that isn't a problem.

Except at high speed (>500 MHz) and/or long traces it isn't drops you need to worry about. It is reflections due to changes in impedance for the trace. This is why sometime clocks will be terminated with a series resistor at the source or a resistor to ground or the 1/2 way voltage at the end.

If you wish to buffer it, there are numerous parts to do that.

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Part datasheet - analog.com/static/imported-files/data_sheets/ADAU1701.pdf – njt Jul 10 '12 at 10:10
Im acually looking at buffering the analog oscillator output OSCO on that part, and using it as the MCLK signal for a pwm stage. There is another way of using the MP11 pin as the MCLK source but im already using it to generate the BCLK for the slave IC. I know the datasheet doesnt recommend it but the analog support guys seem to see this as the most viable solution, outside of having an external clock circuit generating the 12.288mhz. Are there any good examples of a buffered external MCLK in the web? I have a circuit in mind but cant post it on my ipad just now... – njt Jul 10 '12 at 10:12

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