# What “bus turnaround” delay should my PSRAM have?

I have a PSRAM driven by an STM32. One of the timing options for the STM32 is the bus turnaround FSMC_BusTurnAroundDuration. The ARM reference manual (see page 1250) says:

These bits are written by software to insert the bus turnaround delay after a read access only from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive addresses on the databus for the next side-by-side transaction.

Now my PSRAM is not NOR Flash and does not multiplex the data and address lines, so I assumed that FSMC_BusTurnAroundDuration is a "don't care" in my case. However, when I set

FSMC_BusTurnAroundDuration = 0;


then the ARM crashes. Any value between 1 and 15 doesn't crash the ARM.

Why is the bus turn around duration relevant for my PSRAM?

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 The ARM reference manual doesn't have info on the FSMC bus, but the STM32 reference manual does. st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/… – Mark Lakata Nov 2 '12 at 0:54