# MC34063A: Why am I overclocking this chip?

I've decided to get some experience with DC-DC converters and I've obtained an Onsemi MC34063A DC-DC converter. From documentation I've got the datasheet, the AN920 application note and the Excel worksheet. The datasheet mentions one more application note, the AN954/D, but I can't seem to find it anywhere.

The idea was to step-down 12 V to 5 V with currents of up to 500 mA and 50 mV ripple. So I read the formulas in the datasheet, the application note and the worksheet and did some calculations.

I took the $V_{sat}=1.3 \mbox{ } V$ , from the datasheet maximum value, I'm using 1N5817, so at 1 A, $V_{F}=0.45\mbox{ } V$, minimum input voltage, if I take the variation to be 10% is $V_{in(min)}=10.8 \mbox{ } V$, output voltage $V_{out}=5 \mbox{ } V$. Using the formula from the datasheet, this gives me $\frac{t_{on}}{t_{off}}=1.21$. I've selected the frequency for the converter to be 89 kHz, because it's supposed to nicely fit a $220 \mbox{ } pF$ capacitor, but more on that later. Next, $t_{on}+t_{off}=11.24 \mbox{ } \mu s$ which gives me $t_{off}= 5.09 \mbox{ } \mu s$ and $t_{on}=6.15 \mbox{ } \mu s$. All this gives me $C_t=246 \mbox{ } pF$, so I'll use $220 \mbox{ } pF + 22 \mbox{ } pF=242 \mbox{ } pF$. Next, I've got the $I_{pk(swich)}=1 \mbox{ } A$. The sense resistor is $R_{sc}=0.3 \mbox{ } \Omega$, so I'll use 3 times 1 $\Omega$ resistor and connect them in parallel. Next is the minimum inductivity $L_{(min)}=28 \mbox { } \mu H$. Next, there's the output capacitor $C_o=28.1 \mbox{ } \mu F$. Finally there are the output resistors. The formula is $V_{out}=1.25(\frac{R_2}{R_1}+1)$. I picked 4 times $10 \mbox{ } k \Omega$ resistors. One for $R_1$ and 3 in series for $R_2$.

Now let's take a look at the application note and see if they did anything different there: Well the formula for the $R_{sc}$ is a bit different and gives me $0.263 \mbox{ } \Omega$ as the minimum sense resistor value.

Now let's see the Excel worksheet: New parameter $\frac { \Delta I_{L} } {I_{l(avg)} }$ appears there and the worksheet says:

For Maximum Output Current it is suggested that ΔIL should be chosen to be less than 10% of the average inductor current, IL(avg). This will help prevent Ipk (sw) from reaching the current limit threshold set by RSC. If the design goal is to use a minimum inductance value, let ΔIL = 2*IL(avg). This will proportionally reduce output current capability.

Well, I'm not sure what to do here, but high current output sounds nice so I put it to 6% and the worksheet gives me the minimum inductance of $920 \mbox{ } \mu H$. It so happens that I have a 1 mH inductor in my junk-box (DPO-1.0-1000) so I decide to use it.

Finally, I have the schematic:

Now if I understand the operation of this device correctly, the timing capacitor is used to provide clock which is fed to the inductor as needed. If the sense resistor has too high voltage (meaning overcurrent condition) or the consumption is too low, clocks are skipped. As far as I can see, there should be no way for the chip itself to change the frequency set by the capacitor.

My problem seems to be the switching frequency and the way it changes with load. The regulator is in the documentation said to work up to 100 kHz and I'm seeing some strange results on the oscilloscope. I'm measuring the waveform on the diode and on the timing capacitor.

Here's how it looks like with no load:

As far as I know, this type of wave should appear because the regulator is skipping cycles and it should be normal.

Next, I have the load with some LEDs drawing around 200 mA.

Note that the frequency is a bit high. I expected 89 kHz and lower (since the circuit is on a breadboard and I expect there to be parasitic capacitance from neighboring rows), but it's 99.6 kHz, which is right on the limit of normal operation.

Here is what happens when I connect a microcontroller board flashing some LEDs. The frequency is more than twice the maximum operating frequency of the regulator.

Using a $1 \mbox{ } \Omega$ resistor and another power supply, I've determined that the highest instantaneous current from this board is 294 mA, so it's well within the limit of the 500 mA I designed this for. The output ripple is 680 mV peak to peak, so it seems to be more or less fine and the voltage is around 4.9 V, so it too seems to me more or less normal.

So any ideas what's going on with the frequency here? I've tried with various different timing capacitors and they all give similar behavior and none of them give me the calculated frequency.

UPDATE

Here's the oscillogram of the output using the springy type ground lead connector and bare probe tip synchronized with the peak of greatest magnitude :

UPDATE

About the frequency, I found some 10 Ω ceramic resistors and tried loading the supply with one of them (which should give me a 500 mA load), but I still get the high frequencies and it seems to be related somehow to current limiting, from what I can see. When I connect the resistor, the maximum current I can get is around 370 mA. I've experimented with different values of the sense resistors and with increased resistance of sense resistors, the frequency increases.

Here's an example of the $C_t$ waveform with 1 Ω resistor:

and here's with 0.5 Ω sense resistor:

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 Like @Kit said, your output filtering may be the problem. I have never used the famous IC you are using, but I think the output capacitor can be low. Have you tried increasing the capacitor to something like 220uF? By the way, I do not see how 0.68mVpp ripple on the output is fine, when you were aiming for 50mV? – abdullah kahraman Jul 13 '12 at 19:21 That is going to be 680mV, not 0.68mV :) – abdullah kahraman Jul 13 '12 at 19:26 @abdullah kahraman Well, which capacitor should I consider output here? I'm already using 220 μF tantalum as shown by Co in the schematic. At the filter output, I have 22 μF low ESR electrolytic capacitor. Should I work on it? Also the ripple isn't fine at all, but at this point, I'm more concerned about the phenomenon I'm seeing. Unfortunately, I had some exams these days, so I didn't have enough time to work on this question. Interesting thing is that I have more noise after the filter than before the filter. – AndrejaKo Jul 13 '12 at 20:29 Sorry, I thought your output capacitor was 22uF, didn't see the filter in the figure. The filter is optional and controller should work without it, right? It is odd that you have more noise after the filter. Have you tried removing the filter? Also, have you connected your diode's anode directly and shortly on the input capacitor's ground, as @Oli noted? – abdullah kahraman Jul 13 '12 at 20:44 @abdullah kahraman It seems to work better without the filter. Actually Oli mentioned output capacitor, but I'll try with input too and see what happens. – AndrejaKo Jul 13 '12 at 20:48

The breadboard may be causing issues, check your layout (especially the feedback section)

Also, it's possible the inductor you are using is not suitable - it says it's only rated up to 100kHz, so it's SRF (self resonant frequency) is probably pretty low. It may be causing instability.
Try changing it to one with a higher SRF (e.g. >500kHz), but still with suitable current capability.

I did mention the output cap below but abdullah is right about the input cap being important. It does depend on the load, but the whole loop from in to out should be as small and low impedance as possible, ideally using a ground plane. On a breadboard that's "difficult" ;-)
If the frequency problem is not there with a steady load, I think as Kit says it's an output filtering issue, since the switcher won't be fast enough to adapt to high di/dt changes on the output and there's no "reserve". Increase the output filter capacitance and see if the ripple drops, if it does that's almost certainly the issue.

EDIT - Ah, I see you tried it with a resistor on the output.
In that case it would seem it's not the filtering. At this point I think I would use a different method of prototyping that's more suited to a switching regulator. Also use another chip just in case.
Either etch a board or use dead bug style, or stripboard with very careful attention to layout. If the frequency is still too high I would assume it's part of it's operation and not covered correctly in the datasheet - if this is the case then an e-mail to OnSemi is in order to see what they have to say.

EDIT 2 - Okay, after more reading I think the sense resistor (possibly combined with the inductor issue mentioned above) may be causing the current sense to trip too often and increase the timing capacitor charging slope. This will likely appear like the oscillator is switching faster.
A relevant quote from the App note:

When this voltage becomes greater than 330 mV, the current limit circuitry provides an additional current path to charge the timing capacitor CT. This causes it to rapidly reach the upper oscillator threshold, thereby shortening the time of output switch conduction and thus reducing the amount of energy stored in the inductor. This can be observed as an increase in the slope of the charging portion of the CT voltage waveform as shown in Figure 5.

Your oscillscope waveforms seem to agree with this description. Also, if you haven't tried changing the inductor, do this and see how it goes, plus you could try not using the current sense (i.e. just connect to input voltage)

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 What should I be looking at in the feedback section? Right now, it's a bit long since I have 3 1/4 W resistors in series. Should I try to make it shorter? Also nice catch for the inductors. The site for the series claimed 200 kHz operation and I didn't even notice 100 kHz in the datasheet. – AndrejaKo Jul 11 '12 at 4:49 Try and keep the FB short and away from the high current carrying traces. Also try and make your output cap ground to diode ground return loop as small as possible. Basically think about how the current is flowing and try and make the loop area as small as possible. Definitely change the inductor. Switchers can be troublesome on a breadboard, if all else fails solder it onto some stripboard (or even better do it dead bug style over a solid ground plane) and see how it performs. – Oli Glaser Jul 11 '12 at 5:06 I think you got it on the EDIT 2. It is now obvious with the quote from the app note. Also, this may be proved if @AndrejaKo would try the circuit without the sense resistor. Hope this is the issue. – abdullah kahraman Jul 14 '12 at 20:47 I've tried using the chip without the current sense resistor and it seems to be the problem. I'll see if I can get some response from OnSemi. – AndrejaKo Jul 15 '12 at 18:53

My best guess would be the amount of output filtering or possibly the sizing on the R_sc.

Note the comparator feeding back into the and gate which controls the switch in your schematic. If the load current changes and it causes swings in the voltage feedback loop then you could create a virtual increase in the PWM frequency. I don't quite have time to draw out a full graph for you, but basically if current increases in the load causes the switch to turn on (i.e. if you turn on a bunch of leds simultaneously), but then you quickly turn them back on, that will be superimposed on top of the 99.4kHz PWM and make the switching frequency look much higher.

The other thing you might try is making R_sc too big and see what the waveform looks like on a really consistent load. Like you said, the pwm frequency shouldn't change, and the draw should cause the duty cycle to increase slowly because the difference between the output voltage and input voltage should approach 0 as you reach the maximum draw. That way, all the energy is dissipated in the resistor, none in the switching converter at maximum draw. I had a reason I thought this might be an issue, but I'll be honest I think it's the first thing.

Hope that helps! Good luck!

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When dealing with switch-mode converters, you should pay attention to the high $\dfrac{di}{dt}$ paths of the circuit. To determine these problematic paths, one can use the diagram of the topology and draw the states of it. Let's take a look at the circuit diagram for the buck converter, in the different states the switch:

Red lines denote the high current flow. You can see that some parts remain RED in both positions of the switch and some parts change color. The ones that change color are the problematic paths, because the current flows through them change, when the switch changes position. That means they are high $\dfrac{di}{dt}$ parts of the circuit, and require care when designing the layout. Look at my this post on how inductance affects when there is high current change in time. So, what to do?

• Shorten and widen the trace, hence reduce the inductance. However, do not make it wider than it should be, otherwise you will create a bigger antenna for the EMI. Make it wide enough that it will carry the current needed.
• If these traces are connected to the GROUND net, then try to prevent them running on the ground plane or on the ground bus of a breadboard as much as possible. Only suiting path for this scenario, is the path from the anode of the diode to the ground lead of the input capacitor. Connect it directly and shortly.

Also, some of the things that you see in the scope are not really in the circuit itself. They are caused by the long ground lead of the scope probe. Shorten it, like so:

Resource: PCB Layout Guidelines from National Semiconductor

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In addition to all the things above, please, do not breadboard a switch-mode power supply :) – abdullah kahraman Jul 13 '12 at 21:27

I believe "Over-Clocking" is a misnomer. That applies to using a stable external clock to run a digital computer chip faster. It is not the term we use in the "analog world" to define a drift in astable operation of an analog clock. Simple clocks can be made with a Schmitt inverter and a feedback resistor to self oscillate. Adding a small cap. to ground lowers the frequency. Adding a bias resistor to the input alters the duty cycle. If the Rs input voltage drops and the input hysteresis thresholds also tighten at the same time, then if they use a current source, the relaxation frequency will increase. Conversely lower Rs and increasing input voltage seems to increase the spread of astable thresholds and thus lower the frequency.

THe specs for stability of frequency indicate a wide range of 2:1 in f for max:min.

You ought to consult with TI tech support blog or live even if you choose to accept my answer.

Other important factors worth discussing in another topic include;

1. the ripple in your output regulator
2. the ESR of your regulator and storage caps and effective ripple attenuation.
3. your measurement methods using spring probe are essential but SMA or equiv coax. test ports are even better.
4. the effects of SRF of L1 and saturation effects on load regulation.
5. the effects of non-linear ESR of switched LEDs ( like zeners with 1~10Ω ESR) need to be decoupling with inductive series filter or ferrite bead.
6. The inappropriate sharing of analog for regulator with high current pulsed loads to ground.
7. The effects of shielding on feedback, stability and ripple.
8. The understanding of nominal and min:max values and reasons for variances and sensitivity analysis of SMPS
9. The effective use of BODE plots to determine phase margin or gain margin on regulator stability or from component sensitivity
10. The effective communication with TI support on IC misunderstood behavior.

You may want to lower the Fosc with sufficient margin to stay away from the parasitic effects of harmonics on >100KHz.

BTW I strongly agree with Mr Kahraman. You need a ground plane to absorb stray RF to ground & by lowering the common-mode impedance to ground, high impedance cross-talk effects between parts have a higher ratio of attenuation. It also lowers ESR of ground plane and Power source input impedance which may be a significant factor for this question.

"do not breadboard a switch-mode power supply :) – abdullah kahraman"
An exception might be, cost, time avail. but expect it to be a crude functional test with awareness to stray effects. I have made exceptions in the past when designing for 1K/mo production and have to design the board in 5 days from scratch and later found minor changed were needed. I have learned the value of mockup shields and using my finger to test for sensitive parts to stray coupling, leakage etc. All my fingers are calibrated on an RLC meter for at least 3 freq ;)

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