In relation to a previous question, I'm trying to understand the USB 2.0 requirements for inrush current. I understand the basic idea, but a few details are still unclear to me. The specification states, in part, that:
The maximum load (CRPB) that can be placed at the downstream end of a cable is 10 μF in
parallel with 44 Ω. The 10 μF capacitance represents any bypass capacitor directly connected across the VBUS lines in the function plus any capacitive effects visible through the regulator in the device. The 44 Ω resistance represents one unit load of current drawn by the device during connect.If more bypass capacitance is required in the device, then the device must incorporate some form of VBUS surge current limiting, such that it matches the characteristics of the above load.
The USB-IF also provides a description of an inrush current test:
Inrush current is measured for a minimum of 100 milliseconds after attach. Attach is defined at the moment the VBus and ground pins of the plug mate with the receptacle.
Any current exceeding 100 mA during the 100 ms interval is considered part of the inrush current event. The inrush current is divided into regions. A region is an interval where the current exceeds 100 mA until the time the current falls below 100 mA for at least 100 µs. There can be multiple inrush regions during the 100 ms period. Pass/fail is determined by the region having the highest charge.
That is explicit as far as it goes, but it only gives a minimum measurement time, and it doesn't spell out what algorithm is applied to the inrush regions to come up with a pass/fail decision. I think the idea is that during the regions when the current exceeds 100 mA, the current is integrated to get the total charge transferred during this window, and the total charge must not be greater than what you would get with the 10 uF // 44 Ω load. According to one source, this would be 5V * 10 µF = 50 µC. That is where my understanding gets a little shaky.
To help me understand, I analyzed the following circuit:
[The R1 resistance is not part of any specification, but I need it to do the math, and I can let it go to zero as needed.] The current starts at \$V_1/R_1\$ and decays exponentially to \$V_1/(R_1 + R_2)\$ with time constant \$(1/R_1 + 1/R_2)^{-1} C_1\$.
The total charge transferred at time \$t\$ will be
$$ Q(t) = \frac{V_1}{R_1 + R_2}t + \frac{V_1 R_2^2 C}{(R_1 + R_2)^2}\{1 - \exp(\frac{-t}{C_1}(\frac{1}{R_1} + \frac{1}{R_2}) )\} $$
In the limit as \$R_1\$ goes to zero, this simplifies to
$$ Q(t) = \frac{V_1}{R_2} t + V_1 C$$
One part I don't understand is that with 5 volts from the USB bus and the prescribed 44 Ω load, there will always be a 5V/44 Ω = 114 mA current, which is more than the 100 mA limit described in the quoted USB-IF test, and also more than the maximum one unit (i.e. 100 mA) load allowed for a low-power USB function (USB 2.0 spec. section 7.2.1). In the R1 = 0 limiting case, this current will draw as much charge as the capacitor (i.e. 50 µC) in R2*C1 = 440 µs.
So the question, if you're still reading, is what does it mean, precisely, to "[match] the characteristics of the above load" (i.e. 44 Ω parallel with 10 µF), and how does the described USB-IF inrush current test decide how much current is too much?
Thanks.
