Power consumption of unimplemented pins?

Question

New versions of TI's Code composer studio have a lint-like tool which checks the code and provides recommendations on how to modify the code to decrease power consumption. One of the things I've noticed it complains about is the power consumption of pins which aren't set to low.

What caught my interest was the fact that the microcontrolers I was experimenting with have different number of ports depending on the package and the package I used didn't have the port the tool complained about pinned out. In this particular case, I was using MSP430G2553-IN20 and if my information is correct, the IN20 has same core as other versions, but the port 3 isn't connected to any pins.

So my question is: Are there any ways to estimate the power consumption of unimplemented pins in general?

Answer 1

I have no experience with the processor mentioned. The following statements should be true in general unless specific indications to the contrary are given in the data sheet. The following does NOT answer your question with certainty for your specific part but does tell you what may legally happen if you ignore the issue.

If a port exists then the related gates need to be dealt with, pinned out or not.

If the manufacturer provides a power down ability for the port then you can expect the incremental drain to be "in the noise" compared to other processor currents.

If the port is powered but not pinned out then either
the design assigns it as outputs, or as inputs with pull downs or pull ups,
OR you need to deal with it explicitly. If the manufacturer defaults it to some "safe" state you'd hope that the data sheet says so.

If set as terminated inputs (high or low) or as unloaded outputs you'd expect the incremental current to be low - look at figures for active ports for the processor concerned and you'd expect the same or somewhat less (no multiplexer path to pin active).

If set as unterminated inputs (by you or the manufacturer) then current drain can be anywhere from minimal to fatal - a drifting input pin can float to about Vdd/2 with the input gate in the transition state between high and low and an unknown and significant current following the "shoot through" path. The exception are Schmitt input gates whose inputs will behave properly and sit at one or other rail.

While you would hope that an active input gate, that has no multiplexer path to a pin, will be pulled consistently high or low by interior bias current that the design applies, this is not guaranteed and Murphy is allowed to assign such an internal uncommitted input to whatever voltage is worst if you don't beat him to it.

Answer 2

From the TI Ultra-Low Power (ULP) Advisor Wiki:

Known Issues

Notice that ULP Advisor detects the number of ports & GPIO pins on the device basing strictly on the device number and does not have the knowledge on the actual package for the device. Therefore, it always assumes the largest package available to the device. In the event that a smaller package is actually used in the application, certain port pins might not be available on the device package. If this is the case, this remark can be safely ignored as these pins are internally terminated to ensure lowest power consumption and therefore the application is not required to configure/terminate these port pins.