FPGA “physical view” visualiser with Verilog simulation

Question

I find the 'Physical View' provided with most FPGA tools somewhat memorising for a complex design. Tens of thousands of switchboxes, LUTs, latches and multiplexers all configured mysteriously from the HDL. It would be great to combine a logic simulator with the post-P&R layout to animate the physical view with 1/0 signals rippling through the design as stimulus is presented. This would also provide a "visual check" that the trace tools are actually making valid measurements of the timing. A slow motion view could show the clock/data race through the design so you can see the longest path lose the setup race against the clock. It's all physics.

At least it would make an educational video short, and I'm sure the X/A marketing bods would love it. Digital design is fun if you use your imagination.

So, why isn't this done already? Other than the tools are fiendishly complicated already and functional correctness is difficult enough without worrying about animation?

Answer 1

Because it wouldn't add value for their customers. It would only be "eye candy" at best. It is easier to debug at the RTL level than at the gate level. Also simulation is faster at the RTL than the gate/LUT level.