I was learning about the advantages and challenges in scaling down MOS transistors. I came across this statement in Wikipedia :
The main device dimensions are the transistor length, width, and the oxide thickness, each (used to) scale with a factor of 0.7 per node. This way, the transistor channel resistance does not change with scaling, while gate capacitance is cut by a factor of 0.7. Hence, the RC delay of the transistor scales with a factor of 0.7.
Reduction in RC delay means improvement in switching speed.
But as per my understanding, capacitance per unit area is given by the relation C = eps/Tox, where eps is the epsilon and Tox is the oxide thickness. So when Tox is reduced, C increases, which in turn should increase the delay. But what wikipedia says is opposite.
So my question is, how scaling down the transistor reduces the capacitance?
Any good reference or link also will be appreciated.