I'm trying to finally apply what I learned at university in the course of power electronics. However I find that both that course and most of the books / online references are lacking on some points.
In fact (this may be similar to controlling H-bridges for motor drivers, not sure) there are some possibilities concerning how to realize a step-down (buck) converter:
- Using PMOS as input switch (source at supply voltage) -> gate of the PMOS needs to be HIGH when PMOS is off, while gate of the PMOS needs to be LOW when PMOS is on
- Using NMOS as input switch (drain at supply voltage) -> gate of the NMOS must be commanded via boostrapping (needs an additionnal Diode and Capacitor)
Additionnally it may be a good idea to use a synchronous buck converter (less losses) using an NMOS in parallel to the output diode. I think I got this part and - anyway - it's simpler to command since it's an NMOS with its source tied to the ground.
Back to the original question: while I agree that it may be (theoritically) possible to easily control the PMOS transistor, I think it's pretty difficult, expecially with high input voltages.
Consider that I take power from the wall outlet: 230V_RMS at 10A max (but for my applications I will go for much less, 1A max). I'm gonna get a pseudo-DC voltage by using a bridge rectifier (Gretz's bridge) with a capacitor at its output (standard practice). This last voltage will be the input of my DC/DC buck converter.
Hence the problem: using a microcontroller to generate a PWN signal to control the output voltage (GPIO: 3.3V output, or 5V at best) it's not gonna be possible to activate the NMOS or deactivate the PMOS.
I think I need the NMOS's gate voltage needs to be around 5-10V above the supply voltage. I'll have to do the bootstrapping for that, yet I didn't really understand it. That's what basically GATE drivers are made for AFAIK.
As for the PMOS a simpler solution may be to use an inverted PWM signal (D = PWM at level LOW, normally it's the reverse) and control an optocoupler which has its collector connected to the supply voltage (same as the PMOS source's voltage). Collectors able to sustain that voltage exist, yet there may be a better solution.
There aren't many high voltage MOSFET drivers available on the market (let alone at low cost) and I would really like to know how to do this. I think step-down/buck converters are quite common nowadays, so I find it hard that no such products exist. This leads me to believe that I'm not looking at the right components (yet). Or the only solution would be to realize the driver in discrete components? Any product reccomandation / reference to satisfy these requirements?
EDIT: as I said to Oliven Lathrop here is what I have in mind to control the PMOS. Basically I use a BJT as a current source and then shunt just enough of the voltage (12-15V) to get the PMOS in conduction mode. Otherwise ideally no current flows in the BJT and the PMOS is blocked. .
I have not verified the polarity of the PWM signal (should it be reversed or not) but in principle this may "just" work. NPN transistors supporting > 400V_DC are much more common than PNP/PMOS and their price is small. A small current in the BJT is enough. Therefore R2 has to be quite large (in order to get I_BJT_Collector ~ 1mA) and R1 just large enough (but not too much, otherwise the charge takes too long and I dissipate too much energy). May pose a problem for the discharge though, since the accumulated charges can't be evacuated?
EDIT2: I know on the schematic I represented an NMOS transistor, but there was no PMOS symbol in the schematic program I'm currently using. It's actually a PMOS!
EDIT3: On second though I'm not sure this would work since the current is imposed in the NPN, not through R1. It may just work if the current going into the MOS (I_G > 0) adds up with the collector's current of the NPN (I_C > 0). This way the voltage drop actually increases and conduction is assured. Still doubts on the opposide process though.