Negating a number in VHDL using least logic

Question

I want to do something like this:

variable a, b (both signed)
variable error (signed also)

if (a is positive) 
    b = error
else
    b = -error

So far I have something like this:

if (a(a'high) = '0') then
    b <= error;
else
    b <= -1 * error;
end if;

But this doesn't work because the multiplication makes the RHS a larger width.

What is the best way to attack this? I could write a function to do a 2's complement negation and use this, but I'm also rather worried about the effect on timing requirements.

Answer 1

Something like:

variable a: signed(7 downto 0);
variable error: signed(a'range);
variable b: unsigned(a'range);

if a < 0 then
  b:=-error;
else
  b:=error;
end if;

However you do it, the logic should end up the same (even if you multiply by -1, I'd hope the synth is smart enough to notice and just stick a set of LUTs and a carry chain in there!)

Answer 2

begin 

     b <= not(error) + "00000001"; 

end 

There are some edge cases, watch out, read this carefully.

I believe you know it but I'll mention it just in case. bits are bits and the interpretation of them is made by the user, it can be a picture, signal, number, positive number etc. most FPGAs treats numbers as 2's complement.