Every time the master clocks a word's worth of data (normal word length is 8 bits, but some masters are programmable), a word of data will be sent and a word of data will be received. If the slave is "ready" for the data interchange, great. If not, the master will still send a word and receive a word; what will happen as a result depends upon the design of the slave.
A typical hardware slave device will be designed so that even when the device itself is "busy", its SPI hardware will either always be ready to exchange data, or else always be ready to have the master request status by feeding it a falling edge on /CS and clocking in some status-request command. If the device is busy, the hardware might not be able to do anything beyond sending an "I'm busy" response, but if the device sends a response that says "I'm not busy", it's guaranteed to be ready to exchange some amount of data without further delay (the exact amount of data will depend on the device, and possibly upon its reported status). For example, an SPI memory chip might be designed so that once it reports that it is not busy, it will always be ready to send or receive a page worth of data.
Note that many microcontrollers' SPI slave implementations fall way short in this regard. SPI has a very rigid association of incoming and outgoing data bytes; some controllers require that the CPU read each incoming byte and determine the response between the last clock of one byte and the first clock of the next, and send out unspecified data if the CPU fails to react in time. Some others are better in various ways, but many effectively require that the master either guess at when the slave is going to be ready for each byte, or else use another wire for that purpose. Even implementations which use another wire can be problematic, since if the handshake wire reports "ready", the master sends a byte, and the wire continues to report "ready", it may be unclear whether the slave is still ready, or whether the slave isn't ready but hasn't gotten around to setting its wire to indicate "unready". UARTs often include hardware flow control logic that will stop asserting a "ready" line as soon as they're unready, even without CPU intervention, but I've never seen an SPI slave that did so.