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This is related to a few different questions (question 1, question 2).

From question 1, I have a device with rather high decoupling capacitance which exceeds the USB 2.0 10uF device limit. I've tried reducing/limiting these caps as much as possible, but I just can't get below this limit. I believe under normal operation the device should draw less than 1 power unit but I would like to have the ability to request more units if I find 1 is insufficient. I had picked out a chip (NCP380LSN05AAT1G) which was designed for 500mA current limiting with soft start and thermal shutdown.

As I was reading through the datasheet though, it seemed like this chip was meant to be on the host side, not the device side. In particular I'm referring to figure 27 on page 20. Is this something that's usually (or always) present on a laptop/desktop USB 2.0 compliant port? If that's the case do I need to or should I provide unrush current regulation on my device? The device is only ever plugged into a laptop/desktop. What are the consequences of not providing any inrush current regulation on the device?

Typically who's responsibility is it to regulate inrush current? The device, host, or both?

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... do I need to or should I provide unrush current regulation on my device? The device is only ever plugged into a laptop/desktop. What are the consequences of not providing any inrush current regulation on the device?

"Properly" you should provide device side current limiting.

Worst case you can dip the power rail and cause an outage on other connected equipment or cause startup problems with the device you are connecting.

In practice I'd expect that most systems will survive plugging in capacitors substantially greater than 10 uF. However, if this did cause misoperation or even damage in practice you would have no grounds for complaint.

10 uF would have trouble pulling the skin off most rice puddings and even say 100 uF is not a vast amount of capacitance*.

But, if you did want to provide startup protection you should be able to achieve this with 1 x MOSFET, 2 x R, 1 x C and an optional diode.

The MOSFET is in series with the large capacitor - call it C1.
When power is off the MOSFET is off.
Place a resistor R2 across FET d-s to provide some startup current if desired.
Place a timing cap C1 from gate to source and a turn on resistor R1 from gate to supply.
At turn on the MOSFET is off. FET gate rises (or falls depending on whether low side N Channel or high side P Channel) and FET starts to conduct and then is fully conducting. By making R2 suitably low and turn on time delay from R1, C1 long enough the main cap can be charged mainly via R2. This is not essential but without R2 the FET needs to transition from off to on slowly enough not to cause inrush problems (still).

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OTG extension to USB depends explicitly on the fact that device will have <10uF VBUS capacitor. If you violate this you may have troubles with OTG USBs (most likely tablets, phones with USB host capability, maybe even RasPI) –  mazurnification Aug 28 '12 at 7:00
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