# Altera optimisation: “Stuck at GND due to stuck port data_in”

I am compiling Verilog code with the Quartus II compiler, and it seems that almost all my code is being optimised away. The "compilation report" says that many of my registers are being removed during synthesis because

Stuck at GND due to stuck port data_in

or

Stuck at GND due to stuck port clock_enable

What do those obscure messages mean? What is data_in and clock_enable? (They are certainly not some of my signals.)

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You get "Stuck at GND" messages when synthesis tool determines that a particular signal is constant and is never changing. Signals can either get stuck at GND (ground), meaning that they are always low (has a value of 1'b0) or they may stuck at VCC (positive supply voltage) when a signal is constantly asserted high (has a value of 1'b1).

Because the signal is constant, synthesis tools is able to perform certain optimizations that could result in reduced logic up to the point when the whole design is optimized away. For example, let's say your module is getting signal from pin A, inverts it and outputs to pin B. If synthesis tool determines that a signal from pin A is always 1'b1, then it can optimize your module away and just drive 1'b0 to the pin B.

From your description, it seems like data_in is an input to FPGA and clock_enable is some signal that gates the clock (i.e. enables or disables the clock). If you have that clock_enable stuck, everything that is driven by the clock that signal is gating can be pretty much optimized away.

Most likely you have this problem because you are missing a connection for a signal, or you did not specify pin assignments. See PinPlanner manual for more information on how to do pin assignments. You can fire it up right from Quartus and its GUI is pretty straight forward, giving you nice drop-downs for signals & pins etc. If that doesn't help, you will have to dig through synthesis log to get more details about stuck pins and trace their origins until the point when you find unconnected wires and/or buggy logic that makes those stuck signals.

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These signals lower level post-synthesis signals. You could read the first as saying "the data input to a flip-flop is always zero. You don't need this flip flop; I'll just connect 0 to what the flip-flop drives"

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If "almost all" the design is being optimised away you probably have black-box (_bb) models for vendor IP (eg. ethernet, PCIe) specified for synthesis, rather than generated encrypted cores. In the case of PCIe this will leave all the user logic disconnected and ripe for elimination.

In Quartus make sure you have added .qip files to your project rather than _bb.v files. This may vary by the exact core you are using.

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