# cutoff state of transistor

A transistor has an npn junction. It has collector, base and emitter region. For it to be in cutoff, we can make the base lead in open mode. Now, what will be the correct schematic diagram, (showing each pn junction's voltages) of a cut off? thanks

PS: im pertaining to the proper placement of + and - signs in collector-base and base-emitter junctions. if possible, include real valued dc bias

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Perhaps you're asking for a diagram such as this one. –  m.Alin Sep 13 '12 at 12:14

If you're familiar with double-subscript notation, you have your answer at hand.

For example, the base-emitter voltage $v_{BE}$ is positive when the base is more positive than the emitter, i.e., for $v_{BE}$, the $+$ sign is at the base node.

Likewise, the emitter-base voltage $v_{EB}$ is positive when the emitter is more positive than the base, i.e., for $v_{EB}$, the $+$ sign is at the emitter node.

With that in mind, for NPN transistors, the equations are written in terms of $v_{BE}, v_{CB}, v_{CE}$. By KVL, $v_{BE} + v_{CB} = v_{CE}$ so, if you know any two, you know the third.

Now, remembering the structure of NPN transistor, it is the case that the base-emitter junction is forward biased when $v_{BE}$ is positive and the base-collector junction is reverse biased when $v_{CB}$ is positive.

The cutoff region is formally defined as the condition that both junctions are reverse biased: $v_{BE}< 0, v_{CB}>0$

For PNP transistors, simply reverse the order of the subscripts and everything follows through.

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