HDD works in a partly sequential manner. However, RAM is known for random memory access, allowing equal speed of memory access for every location at every time. So, what makes RAM so special? How does random memory access work? (I know that DRAM is not exactly random access, and works in burst. I am not sure what this means also.)
Memory cells are arranged in a matrix
This is a 16-bit memory, 1 bit wide, so it needs 4 address lines to address each individual bit. That's the
The column select does something similar, but uses a multiplexer to select 1 of 2\$^N\$ lines as the output signal. So the combination of row select and column select can address an individual memory cell.
This is Random Access Memory because any bit is directly accessible, no matter what the address is. And it goes for DRAM as well as SRAM. SRAM needs more hardware to store a bit (4 or 6 FETs) than the DRAM shown, which needs only 1 FET per bit. The data is stored in the capacitors. Capacitors have leakage, and after some (very short!) time the data will be gone. That's why DRAM needs frequent refreshing: the data is continuously read and rewritten between accesses. This adds some extra hardware to the device, but a DRAM die is still much smaller than an SRAM die with the same capacity.
A simple RAM can be expressed as (From some note):-
A Static RAM data at its heart has a bistable latching circuitry (usually four or six transistors) to store a single bit while Dynamic RAM uses capacitive method of storage for a single bit(only one transistor and a capacitor).Thus a DRAM is capable of holding memory in more denser way than a SRAM.Since capacitive memory is prone to leaking DRAM requires higher refresh rates to maintain the bit information inside memory cells.
Other answers have measured how RAM works internally, but they haven't yet mentioned how it is fits into a system. The simplest type of RAM to understand is a static asynchronous RAM. Such a device has a number of address pins, a number of data pins, and some control pins which together have three states of interest:
A typical static memory chip will have a few timing constraints, which may be effectively modeled by saying that the various inputs may behave as though they have various (not necessarily constant) delays. A read operation may cause arbitrary (garbage) values to be output briefly on the data pins before the chip starts outputting correct data. To perform a write operation, one must feed the chip a valid address some time before asserting the signals to put the chip into "write" mode, and one must hold the correct data on the data pins for some time after the chip is taken out of "write mode. Meeting these constraints is generally not too hard, however. Many memory chips have an additional state which may be thought of as "get ready to read": the chip continuously determines what value would be output on the data bus if it was asked to output the addressed memory location. If the chip is then asked to output that location, it will be able to supply it much faster than if it had to start "from scratch".
Note that while a typical static memory chip will be wired internally as a row/column grid (as indicated by other answers), and will have about half of its address pins wired to control "row" and half to control "column", a typical dynamic memory chip will use one set of address pins to control both row and column. To access dynamic memory, one must select a row address and then assert a pin called /RAS (Row Address Select). This will both latch a row address and cause that particular row of memory locations to be read to a temporary buffer. One may then use the address pins along with some other control pins to access that temporary buffer in a manner similar to a static RAM. Once one is done with a row, one may should /RAS. This will cause the (possibly modified) contents of the row buffer to be copied back to the corresponding row in the array. Some time after /RAS is released, the memory chip will be ready to receive another row address and have /RAS asserted again.
Note that the act of reading a row from the memory array into the temporary buffer will erase that row from the memory array. Consequently, even if one didn't make any changes to the row buffer, it would still be necessary to write it back to the memory array before one could access another row. Note also that the time required to access a row, and the time between finishing with one row and accessing another, are much longer than the time required to read and write data within the buffer. Although many older microcomputers would always perform the entire sequence "select row; read or write byte; unselect row" for each and every memory access, faster computers will attempt to do as much as possible with each row-select operation (I'll confess some curiosity as to why older computers didn't make more efforts in that regard when accessing memory for things like video display updates, since in many cases video memory could easily have been accessed in groups of two, four, or eight bytes). Further, modern memory devices include features to allow certain operations to be overlapped in many cases (e.g. being able to write a row buffer back to the memory array while a different row is being read).