# How does random memory access of RAM work?

HDD works in a partly sequential manner. However, RAM is known for random memory access, allowing equal speed of memory access for every location at every time. So, what makes RAM so special? How does random memory access work? (I know that DRAM is not exactly random access, and works in burst. I am not sure what this means also.)

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Memory cells are arranged in a matrix

This is a 16-bit memory, 1 bit wide, so it needs 4 address lines to address each individual bit. That's the a3..a0 lines at the left. a0 and a1 enter the green 2-to-4 demultiplexer. An N-input demultiplexer can have 2$^N$ output lines, and the binary input indicates which of those will be active. That's the row select.

The column select does something similar, but uses a multiplexer to select 1 of 2$^N$ lines as the output signal. So the combination of row select and column select can address an individual memory cell.

This is Random Access Memory because any bit is directly accessible, no matter what the address is. And it goes for DRAM as well as SRAM. SRAM needs more hardware to store a bit (4 or 6 FETs) than the DRAM shown, which needs only 1 FET per bit. The data is stored in the capacitors. Capacitors have leakage, and after some (very short!) time the data will be gone. That's why DRAM needs frequent refreshing: the data is continuously read and rewritten between accesses. This adds some extra hardware to the device, but a DRAM die is still much smaller than an SRAM die with the same capacity.

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A simple RAM can be expressed as (From some note):-

RAMs are organised as square arrays of individual bits. There are two decoders, a row and a column decoder, and each one bit memory cell is only enabled when both its row and the column lines are one. In the case of a 256 bit RAM each decoder transforms a four bit binary number into a sixteen bit unary number. Thus, in the square array of one bit memory cells, there will only ever be one cell for which both the row and the column lines are one. Each cell is connected to the same read/write line and data line. The data line is connected to the outside through a two way tri state buffer, such that unless the chip is enabled no data can pass either in or out.

A Static RAM data at its heart has a bistable latching circuitry (usually four or six transistors) to store a single bit while Dynamic RAM uses capacitive method of storage for a single bit(only one transistor and a capacitor).Thus a DRAM is capable of holding memory in more denser way than a SRAM.Since capacitive memory is prone to leaking DRAM requires higher refresh rates to maintain the bit information inside memory cells.

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Other answers have measured how RAM works internally, but they haven't yet mentioned how it is fits into a system. The simplest type of RAM to understand is a static asynchronous RAM. Such a device has a number of address pins, a number of data pins, and some control pins which together have three states of interest:

1. Idle state, in which the signals on the address and data pins are ignored, and the data pins are 'floating'.
2. Write state, in which the device will continuously transfer the signals on the data pins (which will be floating) to the memory location identified by the address pins.
3. Read state, in which the device will continuously endeavor to drive the data pins with the last value written to the memory location identified by the address pins.

A typical static memory chip will have a few timing constraints, which may be effectively modeled by saying that the various inputs may behave as though they have various (not necessarily constant) delays. A read operation may cause arbitrary (garbage) values to be output briefly on the data pins before the chip starts outputting correct data. To perform a write operation, one must feed the chip a valid address some time before asserting the signals to put the chip into "write" mode, and one must hold the correct data on the data pins for some time after the chip is taken out of "write mode. Meeting these constraints is generally not too hard, however. Many memory chips have an additional state which may be thought of as "get ready to read": the chip continuously determines what value would be output on the data bus if it was asked to output the addressed memory location. If the chip is then asked to output that location, it will be able to supply it much faster than if it had to start "from scratch".

Note that the act of reading a row from the memory array into the temporary buffer will erase that row from the memory array. Consequently, even if one didn't make any changes to the row buffer, it would still be necessary to write it back to the memory array before one could access another row. Note also that the time required to access a row, and the time between finishing with one row and accessing another, are much longer than the time required to read and write data within the buffer. Although many older microcomputers would always perform the entire sequence "select row; read or write byte; unselect row" for each and every memory access, faster computers will attempt to do as much as possible with each row-select operation (I'll confess some curiosity as to why older computers didn't make more efforts in that regard when accessing memory for things like video display updates, since in many cases video memory could easily have been accessed in groups of two, four, or eight bytes). Further, modern memory devices include features to allow certain operations to be overlapped in many cases (e.g. being able to write a row buffer back to the memory array while a different row is being read).

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