This should be possible. The configuration that you want is called "multi-master"
Your device can be a slave for most of the time, but when you want it to talk to the EEPROM, you can programmatically switch it to be a master. So long as you follow bus arbitration rules, then this should be fine. A snippet from the above link on what both your I2C masters must do:
a) Being able to follow arbitration logic. If two devices start to
communicate at the same time the one writing more zeros to the bus (or
the slower device) wins the arbitration and the other device
immediately discontinues any operation on the bus.
b) Bus busy detection. Each device must detect an ongoing bus
communication and must not interrupt it. This is achieved by
recognizing traffic and waiting for a stop condition to appear before
starting to talk on the bus.
If you plan to use a multimaster device on a bus it is essential that
all masters are multimasters. A single-master is simply a device,
which does not understand the above mechanisms. If a singlemaster and
a multimaster are connected, the singlemaster may well interrupt the
multimaster causing unpredictable results.
Going over the datasheet for the ATtiny, it looks like there is some support for this. Take a look at the
USISR – USI Status Register in the datasheet and namely these two bits:
• Bit 5 – USIPF: Stop Condition Flag When two-wire mode is selected,
the USIPF Flag is set (one) when a stop condition has been detected.
The flag is cleared by writing a one to this bit. Note that this is
not an interrupt flag. This signal is useful when implementing
two-wire bus master arbitration.
• Bit 4 – USIDC: Data Output
Collision This bit is logical one when bit 7 in the USI Data Register
differs from the physical pin value. The flag is only valid when
two-wire mode is used. This signal is useful when implementing
Two-wire bus master arbitration
So it looks there is enough support to do it, you just have to handle it in software, which will unfortunately make your software more complicated, but I suppose that is the tradeoff expected here. As mentioned, you have to make sure that both your masters adhere to the bus arbitration rules, and I imagine the other chip you're using will have a similar register like the one found in the ATtiny, but make sure it indeed does otherwise this won't be possible.
I left a comment earlier about this too, but here is an alternate suggestion to all of this:
If there is no need for both masters to use the EEPROM, if only the ATTiny needs to use it, then it has its own internal on-chip EEPROM that it can use instead in sizes of 128/256/512 bytes. Is that large enough?