My design is not meeting timing. What can I do?

Question

I am using the Altera Quartus II software to compile Verilog for a Cyclone IV FPGA. In my case, the FPGA is fixed; I cannot get a faster one.

Now one isolated module in my design, which deals with relatively fast clocks, is not meeting timing. I have spent some time trying to simply the code, and understand how the compiler interpreted my code with the "RLT viewer" and "Technology Map Viewer".

Despite that, my design is still not meeting timing by a little. What should I do? Are specific techniques/tricks I can try? Can I ask Quartus II to really try its best to optimize the specific module?

Answer 1

Run design assistant and try to optimize design for speed if Your timing constrains doesn't help You to reach the required times. What frequency do You need and how much do You get? What's the worst path? Give us more information.

What You can do is to optimize all combinatorial logic plus always remember to add several pipeline stages if possible. You can also half the internal clock and transfer required data DDR internally. Tell us more about Your application and critical paths, it would be easier to help You. E.g. I recently had a problem to meet timing of MII/GMII mux for Gig-E.