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Why is it that the produced clock frequency is 6.144 MHz, but internally it (8085 processor) uses only 3.072 MHz. Also what leads to the specific value of 6.144 in a clock.

I found an answer at yahoo.... http://answers.yahoo.com/question/index?qid=20080810090119AAurr2i

but I must admit I didn't still get it it well. Could any of you guys throw out a few lines on this, please?

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the yahoo answer is very very poor. Please forgive me if you know the writer. – Kortuk Sep 19 '10 at 22:17
hmm, Just took Microprocessors this semester, so I have no idea how wrong that could have been. I guess I got the answer here...thank you. – loxxy Sep 20 '10 at 16:50
The MC6800 was even more demanding. It had two clock inputs (phi1, phi2, ca. 180 Deg phase shifted) that needed to be non overlapping, i.e. one phase had to be low for some ns before the other was allowed to rise. There was an extra oscillator IC (MC6810?) to generate those clock signals. – Curd Feb 7 '12 at 11:59
@Curd Nasty timing and it had to swing very close to BOTH the supply rails (rare in those days). pdf.datasheetarchive.com/indexerfiles/Scans-000/… MC6871. MC6810 was a 128 x 8 (!) static RAM chip. – Spehro Pefhany Apr 18 '14 at 4:17
up vote 14 down vote accepted

One reason to divide a clock by two is to obtain an even 50% duty cycle square wave. It may be that the 8085 internally uses both clock edges, and wouldn't function if one half of the cycle happened to be much shorter than the other.

In the days when the 8085 was new, those nice canned oscillators weren't common, and people often cobbled together clock circuits out of discrete crystals, capacitors, and logic gates. Dividing by two ensures that you have equally spaced rising and falling edges.

As for 6.144MHz, you will find that it can be divided by an integer to get common baud rate values, at least up to 38400.

follow up ...

Looking at an Intel data sheet for the 8085, there are three interesting statements

  1. The 8085 incorporates all of the features that the 8224 clock generator and 8228 system controller provided for the 8080A

  2. X1 and X2: Are connected to a crystal, LC or RC network to drive the internal clock generator. The input frequency is divided by 2 to give the processor's internal operating frequency.

  3. CLK: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input period.

So, speculations about using the odd edges of the clock to move stuff around internally aside, it becomes apparent that when they designed the 8085, Intel was replacing the need for a special clock controller by integrating that feature into the chip. Dividing the X1-X2 timebase in half before outputting it as CLK ensures that the system gets a nice even duty cycle, if nothing else.

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often different stages in the microcontroller need to be out of phase due to logic delay. using a higher speed oscillator and dividing down and using the two different edges for different sets of logic can greatly reduce cost of the device. JustJeff is spot on with using an oscillator that is a multiple of standard clock rates. It can make high speed transfers very easy. – Kortuk Sep 19 '10 at 22:19
Are you sure about the duty cycle statement? I was under the impression that an instruction cycle may require multiple clock cycles (e.g. one instruction cycle composed of a fetch cycle and an execute cycle). I'm pretty sure even modern-day PICs have a 4-stage instruction cycle, which is why there's all the Fosc/4 throughout the datasheet – ajs410 Sep 20 '10 at 17:09
@ajs410 - the 8085 would definitely take multiple clock cycles to complete an instruction; all the 8 bit micros from that time (that I am aware of) took at least two clocks to do anything. What I'm referring to here is purely internal to the chip. If you look at block diagrams for these old beasts, you can see they have some internal busses, temporary registers and so forth, and it's these that I speculate might be using both edges. Any external bus cycles would be run between edges of the same polarity. – JustJeff Sep 20 '10 at 21:58

At the time this chip was designed, people used as few transistors as possible in the CPU, to make them small enough to fit on the available chips.

I suspect that practically every "register" (both programmer-visible instruction-set registers and also internal microarchitecture latches) in a CPU of that era stored data in a transparent gated D latch or something similar. Nowadays, there's plenty of transistors on a chip, so it's simpler to use full master-slave D flip-flops, even though they use twice as many transistors.

Many instructions take data from some register A, combine it with some other data with the ALU, and store the result back in register A. That is pretty easy to do if register A is implemented with a full master-slave D flip-flop.

But if register A is a transparent gated D latch, you need non-overlapping clocks. You use a pulse on one clock to store some intermediate result somewhere (while register A holds its output constant), and then a pulse on another clock to load register A with the new value (while the intermediate register holds its output constant).

This requires a 2-phase clock. The easiest way to make a non-overlapping 2-phase clock (in those days when transistors were scarce) was a little external circuit that takes an input clock and divides it by two.

As time went on, people figured out how to pack more and more transistors onto an IC. So people designing CPUs integrated more and more of the stuff around the CPU in a full computer system onto the CPU chip.

Reading between the lines of the Wikipedia clock signal article, I get the impression that the people who designed the 8085 and the 6502 and other chips of that era had just a little more room than the previous generation of integrated CPUs, and they decided the best use of that room was to put that little external circuit on-chip. But they kept all the registers the same gated D latch as before.

So that's why the clock frequency is divided by two. You can think of the first external clock pulse generating a pulse on the phase_one internal clock signal to update that intermediate result register, and the second pulse from the external clock generating a pulse on the phase_two internal clock signal to update the programmer-visible register.

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If a latch will never go more than a few microseconds without being reloaded, one can simplify the circuit even further, so that a "latch" is nothing more than a single-transistor pass-gate and an inverter. – supercat Feb 7 '12 at 15:30
Since writing the above, I looked into the design of the 6502; many of the internal buses are driven unconditionally high on one clock phase, and then during the other clock phase a selected register can pull appropriate bits low. If there are e.g. five registers that can output to the bus, this means that instead of needing a pull-up device for each register's output, the chip can simply use one switched pull-up device and two two series-wired transistors for each register to pull the bus down if appropriate. I would expect the 8085 almost certainly uses similar tricks. – supercat Mar 11 '13 at 16:17

There are lots of reasons to split the instruction cycle into multiple clock cycles. A good example is accessing the main memory bus.

Most modern processors are Von-Neumann architectures; that is, their code and data both exist in the same memory chip. Well, if you want to read an instruction, and that instruction is going to load a variable from memory...that's two memory accesses. But most memory is only single-port (that is, it can only do one read or write per cycle). So how do you read the instruction and read your variable?

The solution is to use a two-stage instruction cycle. The first stage will fetch the instruction from memory, and the second stage can then read (or write!) the variable from main memory.

Some older chips went even further. Back in the day, if your chip had 16-bits of addressable memory, but the external address bus is only 8-bits, then you would be familiar with the Address Latch Enable. One clock cycle sends the upper 8-bits of the 16-bit address, and the next clock cycle sends the lower 8-bits. A third cycle could then read/write the variable from/to memory.

There are other, better reasons to have an instruction cycle that is multiple clock cycles in length. One of the best reasons is pipelining. This is a trick that modern processors use to more fully exploit all the execution units available in a chip; for example, while one instruction is being executed, the next is being fetched at the same time.

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I don't think the OP is asking why you'd spread an instruction across multiple clocks, but rather why the 8085 is designed to require you to feed it a 2X clock (which it then divides internally) as opposed to just taking the intended clock frequency directly. – JustJeff Sep 20 '10 at 22:03
everything you said about instructions is on, though. – JustJeff Sep 20 '10 at 22:33

Clock is nothing but a moment when you want an event to occur. Now, we do not prefer level triggering in digital circuits because when more time is given, interaction may occur between different circuits within the microprocessor leading to short circuits. So we GO FOR EDGE TRIGGERING. Now, the microprocessor doesn't know when edge triggering has occured. It only understands 1 or 0. So a flip flop is required to produce 1 and 0 whenever a clock edge is detected. Thus , it becomes necessary to use a flip flop. As a result the clock frequency is divided by two.

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