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can anybody help me how to build a SIPO (Serial In Parallel Out) register just from the RS or RS edge triggered flip flop circuit?
I have tried to build this, but I think its not working. I simulating it in a LOGO!Soft Comfort, and I can not use a different program because its a school project |
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Constructing an SIPO out of edge-triggered registers probably isn't terribly interesting; constructing one out of level-sensitive latches is a bit more interesting. Edge-triggered registers require about twice as much circuitry as level-sensitive ones, but the conventional method of building shift registers from level-sensitive latches requires two latches per bit. It's possible when constructing a large shift register to use some extra circuitry to reduce this burden; the amount of extra circuitry does not depend upon the number of bits in the register, and could easily "pay for itself" with even a 64-bit register (using some extra circuitry to enable groups of four latches to hold three bits). |
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http://www.cs.smith.edu/~thiebaut/270/datasheets/sn74ls95brev5.pdf A shift register does just that. Pull up the datasheet for a 4-bit shift register, like the one above, and it will show you a diagram of the effective logic by which it accomplishes this |
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