What you're seeing is a timing glitch or race condition. There's a slight difference in the time it takes for the a signal and the b signal to propagate through to the output, so if they're both changed at the same time, you can see a very short pulse at the output before it reaches the final state (which happens to be the same as the initial state for this circuit).
If you delay one of the inputs, it will make this glitch longer because you'd have a short time where the inputs are, say, both 0, instead of having (1,0) and then (0,1) as inputs. You should also realize that in reality, you might not know whether the a signal or the b is propagating faster, and it might even vary in response to temperature or other environmental factors. The simulator has probably just arbitrarily chosen one of the two inputs to process first, resulting in a glitch time equal to the simulator's minimum time step.
The usual way to deal with a glitch like this is simply not clock the result in to the next flip-flop until after all glitches have settled. Meaning, design your circuit with adequate set-up time. The fact that glitches only affect a flip-flop's output if they happen at the same time a clock edge arrives is one reason designing synchronous logic correctly is much easier than designing asynchronous logic.