There are bunch of files needed to run an Aldec simulation. What is the minimum set?
Clearly this must include the Verilog/VHDL source, any testbenchs, and a project file. It also needs to include the list of signals from the waveform window.
Specific files suffixes that may or may not be needed are: adf, aws, cfg, dat, ini, log, mgf, order, rlp, set, wsp, wsw.