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I have tested two transistors in multisim, the first is the default(more of generic) and the second is the 2N3904

here is the first picture with default transistor in placed

enter image description here

and here is the corresponding waveform enter image description here

as you can see, its smooth, but if we use the 2N3904 (available in my local electronic store)

enter image description here

the waveform looks like below

enter image description here

the waveform looks heavily distorted. What should we change in the circuit so that the waveform is the same as the original transistor placed. Thanks

Also, as a side note, what modifications are needed, so that the waveform is not inverted. Thanks

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You have neglected to choose suitable cap values, emitter resistor values and collector values as well as the DC operating point for Ic and Vce. Look at the Vb & Re values you have for example. Vb = 10V, even if we assume Vbe=1V, 9V/8ohms >>> 200mA Ic MAX. try again –  Tony Stewart Nov 23 '12 at 14:32
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You can use 8ohm Re but since the DC drop on Re is small, the input signal must be smaller for linearity. So I changed my design below for a gain of 120 unloaded using Re=8 If you cant see the applet, refresh the page and look for java applet window. goo.gl/zBwyz waves are shown Input, Collector and Out –  Tony Stewart Nov 23 '12 at 16:14
    
no comment on my solution? to make it non-inverting with gain you need 2 stages. –  Tony Stewart Nov 23 '12 at 22:56
    
I'm trying it out. Thnx I'll let u know –  IvanMatala Nov 23 '12 at 23:44
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did u try the java applet window. goo.gl/zBwyz ?? allow a few seconds to load –  Tony Stewart Nov 24 '12 at 0:01
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4 Answers 4

up vote 4 down vote accepted

Transistors are inherently nonlinear. The local feedback from the emitter resistor in a single stage is not enough to fix this, particularly if its value is low.

If you substitute one transistor for another, the load line will change. (And by the way, you have to consider the AC load line separately from the DC one, because AC sees different impedances, both through the base of the transistor and through the surrounding components, such as obviously the capacitor bypass on the emitter).

Although the first trace might look like it is undistorted, looks can be deceiving. A spectrum analysis will show you the distortion products.

You will not get low distortion out of a single stage, unless you keep the signal swing very small, far away from the the voltage rails. Perhaps the ultimate example of "cleanliness" in a single BJT stage would be an emitter follower, with a reasonably small input signal.

If you want a virtually distortion-free amplifier, the usual approach is to combine several stages which have modest gain to produce a high overall gain, and then tame that gain with global negative feedback. Global feedback will correct for all kinds of distortion, such as nonlinearities in the individual stages. It can even nearly eliminate crossover distortion from a class B output stage, so that only a small kink or discontinuity is seen on the waveform.

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how does one create a global feedback. sounds interesting –  IvanMatala Nov 24 '12 at 1:19
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Global feedback hast been known since at least the 1940's and appears in countless amplifier designs, so you just have to study existing circuits from books or elsewhere. A common configuration is to make the first stage of the amplifier a diff amp, so you then have a way to subtract the feedback from the input, amplifying the difference. Op-amp integrated circuits usually have such a stage at the input, followed by massive gain, and many op-amp circuits employ feedback. Speaking of which, you can use an op-amp as your first stage, then bring feedback to the (-) input. –  Kaz Nov 24 '12 at 1:30
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To answer the second question first:

The basic single-transistor voltage amplifier you have simulated is inherently an inverting configuration. This is not actually much of a concern for audio purposes, because our ears can not identify that a waveform is inverted, after all!

Further, if you follow this circuit block with a power amplification block, you have the option of inverting the waveform again. Problem solved.

Now the waveform distortion: This is most probably due to the input signal not being suitably biased to fall within the linear portion of the particular transistor's transfer graph (Please check the datasheet for details, I can't do it right now). By changing the bias resistors R1 and R2 suitably, the input signal can be squarely placed midway in the linear part of the curve, that should eliminate the distortion.

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What, for me, jumps out immediately is the unusually small value for the emitter resistor \$R_e\$.

In order to stabilize the operating point against variations in transistor parameters, \$R_e\$ needs to be "large enough".

The DC bias equation for this circuit is:

\$I_C = \dfrac{V_{BB} - V_{BE}}{\frac{R_{BB}}{\beta}+\frac{R_{e}}{\alpha}}\$

\$V_{BB} = 40V \dfrac{R_1}{R_1 + R_2}\$

\$R_{BB} = R_1 || R_2 \$

For the values you have,

\$I_C = \dfrac{9.35V}{\frac{4.05k \Omega}{\beta}+\frac{8 \Omega}{\alpha}} \$

To have good \$I_C \$ stability against variations in \$\beta\$, the right hand term in the denominator should be much larger than the left hand term.

For example, in your case, look at the variation in \$I_C\$ when \$\beta \$ is doubled:

\$I_C = 192mA \ , \beta = 100 \$

\$I_C = 330mA \ , \beta = 200 \$

This is unacceptable and most likely the reason for the vast difference in behaviour when you changed to a different transistor.

You should increase the value of \$R_e \$ so that variations in \$\beta\$ make insignificant changes to the bias point.

This will reduce \$I_C\$, the DC collector current, which is desirable as Richman points out in his comment.

With a reduced \$I_C\$, you'll want to adjust upwards the value of \$R_C\$ to get the desired DC collector voltage.

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large enough with respect to? by how much larger? 5x,10x? –  IvanMatala Nov 24 '12 at 2:47
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It depends on how much variation in quiescent collector current you can tolerate. Usually, the beta for a transistor is guaranteed to be within a certain range. So, with the formula I give in my answer, you can work out how much variation in collector current occurs over that range. If, say, you want the collector current to vary less than 10%, you want the right hand term to be roughly 10 times the typical value of the left hand term. –  Alfred Centauri Nov 24 '12 at 12:45
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I selected a lower base voltage and removed the bypass capacitor on the emitter then ensured the collector does not saturate for input level. I chose a gain of 20x (Rc/Re) but matched the collector to the load, so the gain is ~ 10. Note this SIM shows the positive and negative peaks are matched due to optimal biasing.

See what happens when you saturate the collector by raising Vb by lowering 60K (right mouse>edit> adjust slider>apply) enter image description here

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when i lowered the 60k, i notice that there is no more sine wave. only straight line –  IvanMatala Nov 24 '12 at 1:06
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Correct. The middle waveform or the Collector DC voltage drops to become saturated. Since the input impedance of Vbe is low, it also affects the collector voltage ( Rin =hFE*Re). So if this were to be useful, the Collector DC must be center biased for the nominal hFe and output is high gain but not stable with hfe, so it has high gain but several non-ideal characteristics. But for hFE = 100, these values perform well. If you reduce V+ from 20 to 9V, then 60K must drop as well. try changing in smaller increments to see the efffects with slider arrows. –  Tony Stewart Nov 24 '12 at 15:23
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