Before I get to my question, here are the specs for the board and synthesis tool I am using:
- Family: Spartan3
- Device: XC3S200
- Speed: -5
- Synthesis Tool: XST
My 4-bit multiplier is in my design's critical path. I would like to reduce the time multiplication takes so I can reduce my critical path and increase my clock frequency.
I can use CoreGEN to instantiate LUT based multipliers, LUT based constant coefficient multipliers, hard multipliers, and hard constant coefficient multipliers (which I think might just be hard multipliers with one input hard wired).
I am thinking that if I use 15 LUT based constant-coefficient multipliers (or maybe 11, can take care of cases 2,4,8 with shifting and 0,1 are trivial) that I can break this critical path down a bit. My design constraints prevent me from pipelining these multipliers; I need them to just integrate into my combinational logic path.
Would this be faster than just using a hard multiplier? Or would a normal LUT based multiplier be faster than either option?